CVSROOT: /home/oc/cvs Module name: ethernet Changes by: mohor 01/10/19 10:46:53 Modified files: bench/verilog : tb_eth_top.v Log message: eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project. -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml