[cvs-checkins] Import

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	minirisc
Changes by:	oc	00/06/19 06:30:03

Log message:
    Initial import.
    
    Status:
    
    Vendor Tag:	rudi
    Release Tags:	alpha
    
    N minirisc/README.txt
    N minirisc/xilinx_primitives.zip
    N minirisc/minirisc/.cvspass
    N minirisc/minirisc/alu.v
    N minirisc/minirisc/presclr_wdt.v
    N minirisc/minirisc/primitives.v
    N minirisc/minirisc/primitives_xilinx.v
    N minirisc/minirisc/README.txt
    N minirisc/minirisc/register_file.v
    N minirisc/minirisc/risc_core.v
    N minirisc/minirisc/risc_core_top.v
    N minirisc/minirisc/xilinx_primitives.zip
    N minirisc/minirisc/scode/hex2v.c
    N minirisc/minirisc/scode/rf1.asm
    N minirisc/minirisc/scode/rf1.rom
    N minirisc/minirisc/scode/rf2.asm
    N minirisc/minirisc/scode/rf2.rom
    N minirisc/minirisc/scode/rf3.asm
    N minirisc/minirisc/scode/rf3.rom
    N minirisc/minirisc/scode/sanity1.asm
    N minirisc/minirisc/scode/sanity1.rom
    N minirisc/minirisc/scode/sanity2.asm
    N minirisc/minirisc/scode/sanity2.rom
    N minirisc/minirisc/scode/tmr_wdt.asm
    N minirisc/minirisc/scode/tmr_wdt.rom
    N minirisc/minirisc/verilog/risc_core/alu.v
    N minirisc/minirisc/verilog/risc_core/presclr_wdt.v
    N minirisc/minirisc/verilog/risc_core/primitives.v
    N minirisc/minirisc/verilog/risc_core/primitives_xilinx.v
    N minirisc/minirisc/verilog/risc_core/register_file.v
    N minirisc/minirisc/verilog/risc_core/risc_core.v
    N minirisc/minirisc/verilog/testbench/prog_mem.v
    N minirisc/minirisc/verilog/testbench/test.v
    N minirisc/scode/hex2v.c
    N minirisc/scode/rf1.asm
    N minirisc/scode/rf1.rom
    N minirisc/scode/rf2.asm
    N minirisc/scode/rf2.rom
    N minirisc/scode/rf3.asm
    N minirisc/scode/rf3.rom
    N minirisc/scode/sanity1.asm
    N minirisc/scode/sanity1.rom
    N minirisc/scode/sanity2.asm
    N minirisc/scode/sanity2.rom
    N minirisc/scode/tmr_wdt.asm
    N minirisc/scode/tmr_wdt.rom
    N minirisc/verilog/risc_core/alu.v
    N minirisc/verilog/risc_core/presclr_wdt.v
    N minirisc/verilog/risc_core/primitives.v
    N minirisc/verilog/risc_core/primitives_xilinx.v
    N minirisc/verilog/risc_core/register_file.v
    N minirisc/verilog/risc_core/risc_core.v
    N minirisc/verilog/risc_core/risc_core_top.v
    N minirisc/verilog/testbench/prog_mem.v
    N minirisc/verilog/testbench/test.v
    
    No conflicts created by this import