[oc] IDE/ATA-5 controller with DMA and Hard Disk support in Verilog?

["Samit Ashdhir" <samit@antares.com>]

Hi,

Has anyone ported Open Cores ATA/ATAPI-5 controller (OCIDEC-3) core in VHDL to
Verilog? If so, could you please provide the same. I'm looking for the version 3
of the OCIDEC in verilog, which has hard disk and DMA support. Or else does
anyone know where it can be fetched from?

Thanks,
Samit

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