Re: [oc] Problem with EDF format

[Rudolf Usselmann <rudi@asics.ws>]

Well, since this is *OpenCores* why don't you post your
design so that we all can take a look at it. May be one of
us will be able to help you !

Cheers,
rudi


On Friday 08 February 2002 05:27 pm, you wrote:
> Hi everyone,
>
>    I am Ramakrishna, from INDIA.
>    I use Xilinx Tool for Synthesis (XST or ISE 3.1i).
>    We are basically working on fairly large design, in which we have a
> set of memories, which we generally replace by EDN files, and then link
> it to the main design separately during the place and route.  This worked
> sucessufully!
>
>    Now the real deal is , we would like to do the same with a design,
> i.e., we would like to synthesize a small part of design and link it to
> the main design similarly, but we were not able to do so.
>   Can any one please suggest if the above procedure is possible, if so,
> please guide me. Our purpose of doing it is to place two parts of the
> design closer to each other in FPGA so as to
> remove glitches, which we have been encountering. Hope I am clear.
>
>   -Thankyou.
>   -Ramakrishna
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