Re: [oc] A 'core server' ?

["Marko Mlinar" <markom@opencores.org>]

> 
> > But why don't you use C?
> 
> 1) C is non-trivial to parse 
The idea was very simple - to write C program which generates
.v or .chdl file.

> 3) (Most exciting)  Scheme corresponds very closely to the
> internal representation used by gcc.  A first step is
> to develop code to translate Scheme to HDL and vice versa.
> The next stage is to glue this code to gcc.  The result is
> ability to develop powerful chips using
> VHDL/Verilog/C/C++/Java/Ada/...  It should also be possible
> to automatically translate between languages.
:)
Personally I don' t believe in C to verilog translators, since it
is then quite impossible to generate good logic from HDL.
Maybe for testbenches.

> I don't think using generators reduces freedom.  As you
> say, any such generator must be GPLed.  It must also be documented.
> It does not have to be difficult to use.  A GUI could
> be provided.  Alternatively, provide a user interface similar
> to the /proc filesystem of linux.  That way you just access
> a core as if it were a HDL file on disk.  Given a HDL to
> Scheme translator, developers should be able to work in
> the HDL of their choice.
If you want to use same RTL (register transfer language) tree
representation as gcc uses internally, it is quite a lot of work to
translate from verilog. How would you translate bunch of 
always constructs? I suppose you need to make whole
HDL simulation for that.

> I would argue against extending HDLs.  Both Verilog
> and VHDL are standards.   By violating standards cores
> become less portable.  A mechanism similar to what you
> suggest is available in VHDL (generate statement),
> but it is not powerful enough to be truly useful.
I don't think portability will be reduced, if we provide links
to binaries at OC website.
I don't like extensions either but I like them more than
other proposals. Since there are some standards, trying to
cover the same things, I think we should use them.

> widths. For example, in an FFT it would be nice to have the
> number of dimensions as a parameter.  A second example,
> all the bit widths in an FFT need to be matched in a particular
> way to obtain the minimum quantisation noise for a given
> amount of hardware resources.  It would be nice to build this
> complex calculation into the generator so the user just needs
> to specify and input width or an output width or even 
> just an SNR.
Of course, I was thinking of the same thing, but examples were
very simple. Why can't you do this using verilog-2000?
I would say, that Verilog generate statement is as powerful as C.
You also have floating point.
What do you think it is not possible to code?

best regards,
    Marko


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