[oc] Core updates: I2C, OCIDEC-1, VGA/LCD

[Richard Herveille <richard@asics.ws>]

Hi All,

The following cores have been updated (verilog versions only)

- I2C: changed ARST_LVL define into parameter
- OCIDEC-1: Changed RST_LVL define into parameter

- VGA/LCD: Major update. Core available is now version 2.
1) Moved Color lookup table inside core
2) Increased achievable pixel clock frequency (almost 2x)
3) Changed video memory address generation
4) Changed port names to be compliant to new naming convention
5) Changed status & control register contents
6) Removed CBAR register
7) and many more .....

Documentation is not yet updated, soon to come

Richard

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