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[oc] Simulating Synthesised VHDL files using Synopsis

To: cores@opencores.org
Subject: [oc] Simulating Synthesised VHDL files using Synopsis
From: rmmy@ee.iitb.ac.in
Date: Mon, 8 Oct 2001 20:06:51 +0200
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Hi all,
  I am doing Masters in VLSI Engineering. I am using Synopsis tool for my project.
  First i have written VHDL behavioral code and then did functional simulation using VHDL System Simulator (VSS).
  Then i synthesised that code and got structural description (netlist). For simulating this synthesised code we have to include some standard simlation libraries (which contains entity-architectures pairs). 
  Can you please tell me what are those simulation libraries and how to inculde them in '.synopsis_vss.setup file'?.
thank you,
regards,
R. Murali Mohan Yadav,
M.Tech (Microelectronics) 
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