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Current Status
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Current Status:
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- Most of RTL design for 32-bit PCI bridge done. Sources available via CVS.
- Design synthesized and tested with Insight's PCI development kit (Spartan II 150k gates, speed grade -5).
- Sample application, bit-stream for Insight's kit etc. also available via CVS.
- Specification is updated (there have been some minor changes).
- Working on verification suite (PCI BFMs).
- Design document will be done after verification suite is finished.
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Available Blocks on the opencores CVS:
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- Verilog RTL sources for 32-bit PCI to WISHBONE bridge.
- Verilog RTL sources for sample application.
- Bit-stream and timing simulation models for sample application (Can be tested with Insight's PCI development kit).
- Also look at PCI blue interface project - its simulation models will probably be used in this project too (thanks to Blue Beaver).
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