This chapter describes the assembler's floatingpoint instructions. See Chapter 3 for a description of the integer instructions. For details on the instruction set beyond the scope of this manual, refer to the Alpha Architecture Reference Manual.
The assembler's floatingpoint instruction set contains the following classes of instructions:
A particular floatingpoint instruction may be implemented in hardware, software, or a combination of hardware and software.
Tables in this chapter show the format for each instruction in the floatingpoint instruction set. The tables list the instruction names and the forms of operands that can be used with each instruction. The specifiers used in the tables to identify operands have the following meanings:
Operand Specifier  Description 
address  A symbolic expression whose effective value is used as an address. 
d_reg  Destination register. A floatingpoint register that receives a value as a result of an operation. 
2d_reg/s_reg  One floatingpoint register that is used as both a destination register and a source register. 
label  A label that identifies a location in a program. 
s_reg,s_reg1,s_reg2  Source registers. Floatingpoint registers whose contents are to be used in an operation. 
val_expr  An expression whose value is a floatingpoint constant. 
The following terms are used to discuss floatingpoint operations:
Term  Meaning 
Infinite  A value of +infinity or infinity. 
Infinity  A symbolic entity that represents values with magnitudes greater than the largest magnitude for a particular format. 
Ordered  The usual result from a comparison, namely: less than (<), equal (=), or greater than (>). 
NaN  Symbolic entities that represent values not otherwise available in floatingpoint formats. (NaN is an acronym for notanumber.) 
Unordered  The condition that results from a floatingpoint comparison when one or both operands are NaNs. 
There are two kinds of NaNs:
Topics addressed in the following sections include:
Floatingpoint instructions operate on the following data types:
Figure 41 shows the memory formats for the single and doubleprecision floatingpoint data types.
The floatingpoint control register (FPCR) contains status and control information. It controls the arithmetic rounding mode of instructions that specify dynamic rounding (d qualifier  see Section 4.1.5 for information on instruction qualifiers) and gives a summary for each exception type of the exception conditions detected by the floatingpoint instructions. It also contains an overall summary bit indicating whether an exception occurred.
Figure 42 shows the format of the floatingpoint control register.
The fields of the floatingpoint control register have the following meaning:
Bits  Name  Description 
63  sum  Summary  records the bitwise OR of the FPCR exception bits (bits 57 to 52). 
6260  raz/ign  ReadAsZero  ignored when written. 
5958  dyn 
Dynamic Rounding Mode  indicates the current rounding mode to be
used by an IEEE floatingpoint instruction that specifies dynamic mode
(d
qualifier).
The bit assignments for this field are as follows:
00  Chopped rounding mode

57  iov  Integer overflow. 
56  ine  Inexact result. 
55  unf  Underflow. 
54  ovf  Overflow. 
53  dze  Division by zero. 
52  inv  Invalid operation. 
510  raz/ign  ReadAsZero  ignored when written. 
The floatingpoint exceptions associated with bits 57 to 52 are described in Section 4.1.3.
Six exception conditions can result from the use of floatingpoint instructions. All of the exceptions are signaled by an arithmetic exception trap. The exceptions are as follows:
If a true result can be exactly represented in a floatingpoint format, all rounding modes map the true result to that value.
The following abbreviations are used in the descriptions of rounding modes provided in this section:
For VAX floatingpoint operations, two rounding modes are provided and are specified in each instruction:
For IEEE floatingpoint operations, four rounding modes are provided:
The first three of the IEEE rounding modes can be specified in the instruction. The last mode, rounding toward plus infinity, can be obtained by setting the floatingpoint control register (FPCR) to select it and then specifying dynamic rounding mode in the instruction.
Dynamic rounding mode uses the IEEE rounding mode selected by the FPCR and is described in Section 4.1.2. Dynamic rounding can be used with any of the IEEE rounding modes.
Alpha IEEE arithmetic does rounding before detecting overflow or underflow.
Many of the floatingpoint instructions accept a qualifier that specifies rounding and trapping modes.
The following table lists the rounding mode qualifiers. See
Section 4.1.4
for a detailed description of the rounding modes.
Rounding Mode  Qualifier  
VAX Rounding Mode  
Normal rounding  (no modifier)  
Chopped  c  
IEEE Rounding Mode  
Normal rounding  (no modifier)  
Plus infinity 
d
(ensure that the
dyn
field of
the FPCR is 11) 

Minus infinity  m  
Chopped  c 
The following table lists the trapping mode qualifiers. See
Section 4.1.3
for a detailed description of the exceptions.
Trapping Mode  Qualifier  
VAX Trap Mode  
Imprecise, underflow disabled  (no modifier)  
Imprecise, underflow enabled  u  
Software, underflow disabled  s  
Software, underflow enabled  su  
VAX ConverttoInteger Trap Mode  
Imprecise, integer overflow disabled  (no modifier)  
Imprecise, integer overflow enabled  v  
Software, integer overflow disabled  s  
Software, integer overflow enabled  sv  


IEEE Trap Mode  
Imprecise, underflow disabled, inexact
disabled 
(no modifier)  
Imprecise, underflow enabled, inexact
disabled 
u  
Software, underflow enabled, inexact
disabled 
su  
Software, underflow enabled, inexact
enabled 
sui  
IEEE Converttointeger Trap Mode  
Imprecise, integer overflow disabled,
inexact disabled 
(no modifier)  
Imprecise, integer overflow enabled,
inexact disabled 
v  
Software, integer overflow enabled,
inexact disabled 
sv  
Software, integer overflow enabled,
inexact enabled 
svi 
Table 41 lists the qualifier combinations that are supported by one or more of the individual instructions. The values in the Number column are referenced in subsequent sections to identify the combination of qualifiers accepted by the various instructions.
Number  Qualifiers 
1  c, u, uc, s, sc, su, suc 
2  c, m, d, u, uc, um, ud, su, suc, sum, sud, sui, suic, suim, suid 
3  s 
4  su 
5  sv, v 
6  c, v, vc, s, sc, sv, svc 
7  c, v, vc, sv, svc, svi, svic, d, vd, svd, svid 
8  c 
9  c, m, d, sui, suic, suim, suid 
Floatingpoint load and store instructions load values and move data between memory and floatingpoint registers.
Table 42 lists the mnemonics and operands for instructions that perform floatingpoint load and store operations. The table is divided into groups of functionally related instructions. The operands specified within a particular group apply to all of the instructions contained in that group.
Instruction  Mnemonic  Operands 
Load F_floating
Load G_floating (Load D_floating) Load S_floating (Load Longword) Load T_floating (Load Quadword) 
ldf ldg lds ldt 
d_reg,address 
Load Immediate F_floating
Load Immediate D_floating Load Immediate G_floating Load Immediate S_floating (Load Longword) Load Immediate T_floating (Load Quadword) 
ldif
ldid ldig ldis ldit 
d_reg,val_expr 
Store F_floating
Store G_floating (Store D_floating) Store S_floating (Store Longword) Store T_floating (Store Quadword) 
stf stg sts stt 
s_reg,address 
Table Notes:
Table 43 describes the operations performed by floatingpoint load and store instructions.
The load and store instructions are grouped by function. Refer to Table 42 for the instruction names.
Instruction  Description 
Load Instructions
(ldf, ldg, lds, ldt, ldif, ldid, ldig, ldis, ldit) 
Load eight bytes (G_, D_, and T_floating formats) or four bytes (F_ and S_floating formats) from the specified effective address into the destination register. The address must be quadword aligned for 8byte load instructions and longword aligned for 4byte load instructions. 
Store Instructions
(stf, stg, sts, stt) 
Store eight bytes (G_, D_, and T_floating formats) or four bytes (F_ and S_floating formats) from the source floatingpoint register into the specified effective address. The address must be quadword aligned for 8byte store instructions and longword aligned for 4byte store instructions. 
Floatingpoint arithmetic instructions perform arithmetic and logical operations on values in floatingpoint registers.
Table 44 lists the mnemonics and operands for instructions that perform floatingpoint arithmetic and logical operations. The table is divided into groups of functionally related instructions. The operands specified within a particular group apply to all of the instructions contained in that group.
The Qualifiers column in
Table 44
refers to one or more trap or rounding modes as specified in
Table 41.
Instruction  Mnemonic  Qualifiers  Operands 
Floating Clear  fclr    d_reg 
Floating Absolute Value
Floating Negate Negate F_floating Negate G_floating Negate S_floating Negate T_floating 
fabs
fneg negf negg negs negt 

 3 3 4 4 
s_reg, d_reg
or d_reg/s_reg 
Add F_floating
Add G_floating Add S_floating Add T_floating Divide F_floating Divide G_floating Divide S_floating Divide T_floating Multiply F_floating Multiply G_floating Multiply S_floating Multiply T_floating Subtract F_floating Subtract G_floating Subtract S_floating Subtract T_floating 
addf
addg adds addt divf divg divs divt mulf mulg muls mult subf subg subs subt 
1
1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 
s_reg1, s_reg2, d_reg
or d_reg/s_reg1, s_reg2 
Convert Quadword
to Longword
Convert Longword to Quadword Convert G_floating to Quadword Convert T_floating to Quadword Convert Quadword to F_floating Convert Quadword to G_floating Convert Quadword to S_floating Convert Quadword to T_floating Convert D_floating to G_floating Convert G_floating to D_floating Convert G_floating to F_floating Convert T_floating to S_floating Convert S_floating to T_floating 
cvtql
cvtlq cvtgq cvttq cvtqf cvtqg cvtqs cvtqt cvtdg cvtgd cvtgf cvtts cvtst 
5
 6 7 8 8 9 9 1 1 1 2 3 
s_reg, d_reg
or d_reg/s_reg 
Table 45
describes the operations performed by floatingpoint load and
store instructions.
The arithmetic instructions are grouped by function.
Refer to
Table 44
for the instruction names.
Instruction  Description 
Clear Instruction
(fclr) 
Clear the destination register. 
Absolute Value Instruction
(fabs) 
Compute the absolute value of the contents of the source register and put the floatingpoint result in the destination register. 
Negate Instructions
(fneg, negf, negg, negs, negt) 
Compute the negative value of the contents of s_reg or d_reg and put the specified precision floatingpoint result in d_reg. 
Add Instructions
(addf, addg, adds, addt) 
Add the contents of s_reg or d_reg to the contents of s_reg2 and put the result in d_reg. When the sum of two operands is exactly zero, the sum has a positive sign for all rounding modes except round toward infinity. For that rounding mode, the sum has a negative sign. 
Divide Instructions
(divf, divg, divs, divt) 
Compute the quotient of two values. These instructions divide the contents of s_reg1 or d_reg by the contents of s_reg2 and put the result in d_reg. If the divisor is a zero, an error is signaled if the dividebyzero exception is enabled. 
Multiply Instructions
(mulf, mulg, muls, mult) 
Multiply the contents of s_reg1 or d_reg with the contents of s_reg2 and put the result in d_reg. 
Subtract Instructions
(subf, subg, subs, subt) 
Subtract the contents of s_reg2 from the contents of s_reg1 or d_reg and put the result in d_reg. When the difference of two operands is exactly zero, the difference has a positive sign for all rounding modes except round toward infinity. For that rounding mode, the sum has a negative sign. 
Conversion Between Integer Formats Instructions
(cvtql, cvtlq) 
Convert the integer contents of s_reg to the specified integer format and put the result in d_reg. If an integer overflow occurs, the truncated result is stored in d_reg and, if enabled, an arithmetic trap occurs. 
Conversion from FloatingPoint to Integer Format Instructions
(cvtgq, cvttq) 
Convert the floatingpoint contents of s_reg to the specified integer format and put the result in d_reg. If an integer overflow occurs, the truncated result is stored in d_reg and, if enabled, an arithmetic trap occurs. 
Conversion from Integer to FloatingPoint Format Instructions
(cvtqf, cvtqg, cvtqs, cvtqt) 
Convert the integer contents of s_reg to the specified floatingpoint format and put the result in d_reg. 
Conversion Between FloatingPoint Formats Instructions
(cvtdg, cvtgd, cvtgf, cvtts, cvtst) 
Convert the contents of s_reg to the specified precision, round according to the rounding mode, and put the result in d_reg. If an overflow occurs, an unpredictable value is stored in d_reg and a floatingpoint trap occurs. 
Floatingpoint relational instructions compare two floatingpoint values.
Table 46 lists the mnemonics and operands for instructions that perform floatingpoint relational operations. Each of the instructions can take an operand in any of the forms shown.
The Qualifiers column in
Table 46
refers to one or more trap or rounding modes as specified in
Table 41.
Instruction  Mnemonic  Qualifiers  Operands 
Compare G_floating
Equal
Compare G_floating Less Than Compare G_floating Less Than or Equal Compare T_floating Equal Compare T_floating Less Than Compare T_floating Less Than or Equal Compare T_floating Unordered 
cmpgeq
cmpglt cmpgle cmpteq cmptlt cmptle cmptun 
3
3 3 4 4 4 4 
s_reg1, s_reg2, d_reg
or d_reg/s_reg1, s_reg2 
Table 47
describes the relational instructions supported by the assembler.
The relational instructions are grouped by function. Refer to
Table 46
for the instruction names.
Instruction  Description 
Compare Equal Instructions
(cmpgeq, cmpteq) 
Compare the contents of s_reg1 with the contents of s_reg2. If s_reg1 equals s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values. 
Compare Less Than Instructions
(cmpglt, cmptlt) 
Compare the contents of s_reg1 with the contents of s_reg2. If s_reg1 is less than s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values. 
Compare Less Than or Equal Instructions
(cmpgle, cmptle) 
Compare the contents of s_reg1 with the contents of s_reg2. If s_reg1 is less than or equal to s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values. 
Compare Unordered Instruction
(cmptun) 
Compare the contents of s_reg1 with the contents of s_reg2. If either s_reg1 or s_reg2 is unordered, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values. 
Floatingpoint move instructions move data between floatingpoint registers.
Table 48 lists the mnemonics and operands for instructions that perform floatingpoint move operations. The table is divided into groups of functionally related instructions. The operands specified within a particular group apply to all of the instructions contained in that group.
Instruction  Mnemonic  Operands 
Floating Move  fmov  s_reg,d_reg 
Copy Sign
Copy Sign Negate Copy Sign and Exponent Move if Equal to Zero Move if Not Equal to Zero Move if Less Than Zero Move if Less Than or Equal to Zero Move if Greater Than Zero Move if Greater Than or Equal to Zero 
cpys
cpysn cpyse fcmoveq fcmovne fcmovlt fcmovle fcmovgt fcmovge 
s_reg1, s_reg2, d_reg
or d_reg/s_reg1, s_reg2 
Table 49 describes the operations performed by move instructions. The move instructions are grouped by function. Refer to Table 48 for the instruction names.
Instruction  Description 
Move Instruction
(fmov) 
Move the contents of s_reg to d_reg. 
Copy Sign Instruction
(cpys) 
Fetch the sign bit of s_reg1 or d_reg, combine it with the exponent and fraction of s_reg2, and copy the result to d_reg. 
Copy Sign Negate Instruction
(cpysn) 
Fetch the sign bit of s_reg1 or d_reg, complement it, combine it with the exponent and fraction of s_reg2, and copy the result to d_reg. 
Copy Sign and Exponent Instruction
(cpyse) 
Fetch the sign and exponent of s_reg1 or d_reg, combine them with the fraction of s_reg2, and copy the result to d_reg. 
Move If Instructions
(fcmoveq, fcmovne, fcmovlt, fcmovle, fcmovgt, fcmovge) 
Compare the contents of s_reg1 or d_reg against zero. If the specified condition is true, the contents of s_reg2 is copied to d_reg; otherwise, d_reg is unchanged. 
Floatingpoint control instructions test floatingpoint registers and conditionally branch.
Table 410 lists the mnemonics and operands for instructions that perform floatingpoint control operations. The specified operands apply to all of the instructions listed in the table.
Instruction  Mnemonic  Operands 
Branch Equal to Zero
Branch Not Equal to Zero Branch Less Than Zero Branch Less Than or Equal to Zero Branch Greater Than Zero Branch Greater Than or Equal to Zero 
fbeq
fbne fblt fble fbgt fbge 
s_reg,label 
Table 411 describes the operations performed by control instructions. The control instructions are grouped by function. Refer to Table 410 for instruction names.
Instruction  Description 
Branch Instructions
(fbeq, fbne, fblt, fble, fbgt, fbge) 
The contents of the source register are compared with zero. If the specified relationship is true, a branch is made to the specified label. 
Floatingpoint specialpurpose instructions perform miscellaneous tasks.
Table 412 lists the mnemonics and operands for instructions that perform floatingpoint specialpurpose operations.
Instruction  Mnemonic  Operands 
Move from FP Control Register  mf_fpcr  d_reg 
Move to FP Control Register  mt_fpcr  s_reg 
No Operation  fnop  (none) 
Table 413 describes the operations performed by floatingpoint specialpurpose instructions.
Instruction  Description 
Move to FPCR Instruction
(mf_fpcr) 
Copy the value in the specified source register to the floatingpoint control register (FPCR). 
Move from FPCR Instruction
(mt_fpcr) 
Copy the value in floatingpoint control register (FPCR) to the specified destination register. 
No Operation Instruction
(fnop) 
This instruction has no effect on the machine state. 