HP Jornada 720 Hardware Configuration ------------------------------------- Version 0.20 2003/03/03 Modified: 2000/01/08 jca (original) 2002/02/05 jca (for touchscreen) 2003/03/03 jca (prepare for release) Copyright Notice ---------------- The information in this publication is subject to change without notice. HEWLETT-PACKARD CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR INCIDENTAL OR CONSQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL. THIS INFORMATION IS PROVIDED "AS IS" AND HEWLETT-PACKARD CORPORATION DISCLAIMS ANY WARRANTIES, EXPRESS, IMPILED OR STATUTORY, AND EXPRESSLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, GOOD TITLE AND AGAINST INFRINGEMENT. This publication contains information protected by copyright. No part of this publication may be photocopied or reproduced in any form without prior written consent from Hewlett-Packard Corporation. (c) 2000-2003 Hewlett-Packard Corporation All rights reserved. ARM and StrongARM are registered trademarks of ARM Ltd. Other product names mentioned herein may be trademarks and/or registered trademarks of their respective companies. ----------------------------------------------------------------------------- 1. Introduction This document briefly describes the hardware configuration and peripherial interfaces on the Hewlett-Packard Jornada 720 Handheld Computer. This document is intended for the sole purpose of porting software to the HP Jornada 720 and has restricted distribution. 2. Memory Map The memory space of the Jornada 720 is as follows: System Flash/ROM (32MB) 0x00000000 Boot Flash/ROM (1MB) 0x10000000 // Ignore this if you don't have debug board Debug CL-CD1284 Registers 0x1A000000 // Ignore this if you don't have debug board SA1111 Registers 0x40000000 EPSON Registers 0x48000000 EPSON Frame Buffer (512KB) 0x48200000 System DRAM (32MB) 0xC0000000 SA1110 Serial port mapping: Port 0 USB Port 1 not used Port 2 IR Port 3 Serial UART port Port 4 SSP port to talk to the microcontroller. Control registers on the SA-1110 must be set to the following values during initialization: Peripherial pin configuration: GPDR 0x0B3A0900 GPSR 0x02100800 GPCR 0x092A0100 GAFR 0x08600000 GFER 0x00048000 GRER 0x00048002 PPAR 0x00000000 PPDR 0x000049FF PPSR 0x00000870 Memory Controller: MSC0 0xFFF04F78 MSC1 0xFFF8FFF0 MSC2 0x201D2959 MECR 0x98C698C6 MDREFR 0x307402A1 MDCAS00 0x5555557F MDCAS01 0x55555555 MDCAS02 0x55555555 MDCAS20 0x5555557F MDCAS21 0x55555555 MDCAS22 0x55555555 MDCNFG 0x72547255 Miscellaneous TUCR 0xA0000000 3. Configuring the SA1111 3.1. Initialization of SA1111 Please refer to the PocketPC sample code that is found on the Intel web site. In the SA1110PPCDrivers.zip file, please look at the file /SA11x0bd/KERNEL/hal/arm/Fwsarm.s, and you'll find the following piece of code: #define TUCR_VAL 0x20000400 #define SKCR_INIT 0x00002081 /* Turn off VCO to enable PLL, set Ready En and enable nOE assertion from DC */ #define SKCR_RCLK 0x00002083 /* Add turning on RCLK to above */ #define SKCR_VAL 0x0000001B /* sets the 1101 control register to on */ TUCR = TUCR_VAL; /* set the oscillator out to the SA-1101 */ // Need to add code here to reset SA1111 // Set GPIO 20 of the SA1110 to high // Wait for 1 us // Set GPIO 20 of the SA1110 to low // Wait for 1 us // Set GPIO 20 of the SA1110 to high // Wait for 20 us SKCR = SKCR_INIT; /* Turn on the PLL, enable */ /* Ready and enable nOE assertion from DC */ mov r0,#0x80000 70 subs r0,r0,#1 /* wait for PLL to settle */ bne %b70 SKCR = SKCR_RCLK; /* turn on the RCLOCK */ SMCR = 0x35; /* initialize the SMC (debug SA-1111 reset */ PCCR = 0; /* initialize the S2MC (debug SA-1111 reset) */ Please also set the following SA1111 GPIO registers after the SA1111 initialization: PA_DDR = 0; PA_DWR = 0; PA_SDR = 0; PA_SSR = 0; PB_DDR = 0; PB_DWR = 0x01; PB_SDR = 0; PB_SSR = 0; PC_DDR = 0x88; PC_DWR = 0x20; PC_SDR = 0; PC_SSR = 0; 3.2. PCMCIA and CF power PCMCIA power is at GPIO A bit 1 of SA1111, set to turn on power For PCMCIA you can choose to power it at 3V or at 5V. The GPIO to be set is GPIO A bit 2 of SA1111, set it to choose 3V and clear it to choose 5V CF power is at GPIO A bit 3 of SA1111, set to turn on power 3.3. Sound interface A Philips UDA1344 chip connected to the I2S and L3 port on SA1111. The speaker is LDD4. The microphone is LDD3. 4. Microprocessor control unit (MCU) The MCU is connected to the SSP port of the CPU. It basically uses the Motorola SPI protocol to communicate to the CPU. 4.1. Reset the MCU To reset the MCU, set the LFCLK bit on PPC register low for 3 microseconds. The MCU will need some time before it is up and running. Will update on the time required later. Initialize the serial interface. mccr0 = 0; // Disable the MCP sscr0 = 0x0387; // turn on SSP with 8 bit Mot SPIs // bit rate 460800 sscr1 = 0x18; // SPH & SPO on 4.2. The communication protocol This is a generic protocol that should be used for all communication between the MCU and CPU. The communication is always driven from CPU side. 1. First the CPU has to wake up the MCU by setting GPIO 25 to low. It has to remain low through out the whole communication session. 2. Before sending every byte, has to wait for GPIO 10 to go low. After GPIO 10 is low, then send the data out. The SPI is duplex protocol, so anytime you send something you will get something, and to get something you have to send something. Please use the TxDummy when you have nothing to send but need to get data back. 3. After all bytes have been transferred, set GPIO 25 to high. An important thing to note, before transmitting and after receiving, all the data need to be bit inverted, because the LSB and MSB for the CPU and MCU are the opposite of each other. The inversions need to be done within the bytes that are sent and received. Here's an example: to send 0xCA, it needs to be shuffled to 0x53 and then send out through the SPI, and when receiving 0x55, the actual data is 0xAA. 4.3. Keyboard Whenever there is new key being pressed or released, there will be an interrupt on GPIO 0. The active interrupt polarity is falling edge. After receiving the interrupt, send out the GetScanKeyCode command, the first byte received should be a TxDummy byte, next send out TxDummy byte and the byte received is the number of key codes that need to be fetched. Then send out the required number of TxDummy to retrieve all the key codes. The key down scan codes start from 0x00 to 0x7F, the key up scan codes are the key down scan code plus 0x80. Here's the list of the key down scan key codes: 0x01 Escape 0x02 Quick Launch 1 0x03 Quick Launch 2 0x04 Quick Launch 3 0x05 Quick Launch 4 0x06 Quick Launch 5 0x07 Quick Launch 6 0x08 Quick Launch 7 0x09 Quick Launch 8 0x0A Quick Launch 9 0x0B Quick Launch 10 0x0C Quick Launch 11 0x0D Volume down button 0x0E Volume up button 0x0F Play button 0x11 '1' 0x12 '2' 0x13 '3' 0x14 '4' 0x15 '5' 0x16 '6' 0x17 '7' 0x18 '8' 0x19 '9' 0x1A '0' 0x1B '-' 0x1C '=' 0x21 'q' 0x22 'w' 0x23 'e' 0x24 'r' 0x25 't' 0x26 'y' 0x27 'u' 0x28 'i' 0x29 'o' 0x2A 'p' 0x2B '\' 0x2C backspace 0x31 'a' 0x32 's' 0x33 'd' 0x34 'f' 0x35 'g' 0x36 'h' 0x37 'j' 0x38 'k' 0x39 'l' 0x3A ';' 0x41 'z' 0x42 'x' 0x43 'c' 0x44 'v' 0x45 'b' 0x46 'n' 0x47 'm' 0x48 ',' 0x49 '.' 0x4B ''' 0x4C Carriage return 0x51 Tab 0x53 Left Shift 0x5A Up 0x5C Right Shift 0x65 Alt 0x66 Fn 0x69 Left 0x6A Down 0x6B Right 0x71 Win key 0x72 Control 0x74 Space 0x78 '/' 0x79 Delete 0x7F On/Off 4.4. Touch The pen status should be monitored on GPIO 9. When the pen is down, GPIO 9 is low, and when there's a new ADC samples for the CPU to collect from MCU, the GPIO 9 will be pulsed (i.e. goes high and low). So the CPU should collect data whenever it detect a falling edge on GPIO 9. GPIO 9 will go back high when the pen is up. To collect the ADC samples from MCU, send out GetTouchSamples and 8 TxDummy. Here's the returned data format: Command Sent | Data received --------------------|-------------- GetTouchSamples | TxDummy TxDummy | 8bit loword X sample 1 TxDummy | 8bit loword X sample 2 TxDummy | 8bit loword X sample 3 TxDummy | Combined X sample bits (lsbs of samples) TxDummy | 8bit loword Y sample 1 TxDummy | 8bit loword Y sample 2 TxDummy | 8bit loword Y sample 3 TxDummy | Combined Y sample bits (msbs of samples) The combined sample bits consist of bit 8 and bit 9 for sample 1, 2, and 3. Bit 0 and 1 are bit 8 and 9 of sample 1, Bit 2 and 3 are bit 8 and 9 of sample 2, Bit 4 and 5 are bit 8 and 9 of sample 3. Bit 6 and 7 are not used and should be ignored. 4.5. Battery To get the battery data, send out GetBatteryData and 3 TxDummy. Here's the returned data format: Command Sent | Data received --------------------|-------------- GetBatteryData | TxDummy TxDummy | 8bit loword main battery data TxDummy | 8bit loword backup battery data TxDummy | Combined battery sample bits The combined sample bits consist of bit 8 and bit 9 for main battery data and backup battery data. Bit 0 and 1 are bit 8 and 9 of main battery data. Bit 2 and 3 are bit 8 and 9 of backup battery data. Bit 4-7 are not used and should be ignored. 4.6. Brightness and Contrast The brightness and contrast is controlled by the PWM in the MCU. To set the brightness, send SetBrightness and the 8 bit brightness value. To get the current brightness value, send GetBrightness and one TxDummy to get the value. The same works for contrast by sending the right command. The PWM for the brightness and contrast can be turned off independently or together with one command. 4.7. MCU Command values #define TxDummy 0x11 #define ErrorCode 0x00 /* PWM Commands */ #define GetContrast 0xD0 #define SetContrast 0xD1 #define GetBrightness 0xD2 #define SetBrightness 0xD3 #define ContrastOff 0xD8 #define BrightnessOff 0xD9 #define PWMOff 0xDF /* Keyboard Commands */ #define GetScanKeyCode 0x90 /* Battery Commands */ #define GetBatteryData 0xC0 /* Touch Commands */ #define GetTouchSamples 0xA0 #define TxDummy 0x11 #define ErrorCode 0x00 5. Display Set the Epson register, which register address is in the first column, with value indicated in the second column. 0x0001,0x00, // Miscellaneous Register 0x01fc,0x00, // Display Mode Register 0x0004,0x00, // General IO Pins Configuration Register 0x0008,0x00, // General IO Pins Control Register 0x0010,0x01, // Memory Clock Configuration Register 0x0014,0x11, // LCD Pixel Clock Configuration Register 0x0018,0x01, // CRT/TV Pixel Clock Configuration Register 0x001c,0x01, // MediaPlug Clock Configuration Register 0x001e,0x01, // CPU To Memory Wait State Select Register 0x0020,0x00, // Memory Configuration Register 0x0021,0x45, // DRAM Refresh Rate Register 0x002a,0x01, // DRAM Timings Control Register 0 0x002b,0x01, // DRAM Timings Control Register 1 0x0030,0x1c, // Panel Type Register 0x0031,0x00, // MOD Rate Register 0x0032,0x4f, // LCD Horizontal Display Width Register 0x0034,0x07, // LCD Horizontal Non-Display Period Register 0x0035,0x01, // TFT FPLINE Start Position Register 0x0036,0x0b, // TFT FPLINE Pulse Width Register 0x0038,0xef, // LCD Vertical Display Height Register 0 0x0039,0x00, // LCD Vertical Display Height Register 1 0x003a,0x13, // LCD Vertical Non-Display Period Register 0x003b,0x0b, // TFT FPFRAME Start Position Register 0x003c,0x01, // TFT FPFRAME Pulse Width Register 0x0040,0x05, // LCD Display Mode Register 0x0041,0x00, // LCD Miscellaneous Register 0x0042,0x00, // LCD Display Start Address Register 0 0x0043,0x00, // LCD Display Start Address Register 1 0x0044,0x00, // LCD Display Start Address Register 2 0x0046,0x80, // LCD Memory Address Offset Register 0 0x0047,0x02, // LCD Memory Address Offset Register 1 0x0048,0x00, // LCD Pixel Panning Register 0x004a,0x00, // LCD Display FIFO High Threshold Control Register 0x004b,0x00, // LCD Display FIFO Low Threshold Control Register 0x0050,0x4f, // CRT/TV Horizontal Display Width Register 0x0052,0x13, // CRT/TV Horizontal Non-Display Period Register 0x0053,0x01, // CRT/TV HRTC Start Position Register 0x0054,0x0b, // CRT/TV HRTC Pulse Width Register 0x0056,0xdf, // CRT/TV Vertical Display Height Register 0 0x0057,0x01, // CRT/TV Vertical Display Height Register 1 0x0058,0x2b, // CRT/TV Vertical Non-Display Period Register 0x0059,0x09, // CRT/TV VRTC Start Position Register 0x005a,0x01, // CRT/TV VRTC Pulse Width Register 0x005b,0x10, // TV Output Control Register 0x0060,0x03, // CRT/TV Display Mode Register 0x0062,0x00, // CRT/TV Display Start Address Register 0 0x0063,0x00, // CRT/TV Display Start Address Register 1 0x0064,0x00, // CRT/TV Display Start Address Register 2 0x0066,0x40, // CRT/TV Memory Address Offset Register 0 0x0067,0x01, // CRT/TV Memory Address Offset Register 1 0x0068,0x00, // CRT/TV Pixel Panning Register 0x006a,0x00, // CRT/TV Display FIFO High Threshold Control Register 0x006b,0x00, // CRT/TV Display FIFO Low Threshold Control Register 0x0070,0x00, // LCD Ink/Cursor Control Register 0x0071,0x01, // LCD Ink/Cursor Start Address Register 0x0072,0x00, // LCD Cursor X Position Register 0 0x0073,0x00, // LCD Cursor X Position Register 1 0x0074,0x00, // LCD Cursor Y Position Register 0 0x0075,0x00, // LCD Cursor Y Position Register 1 0x0076,0x00, // LCD Ink/Cursor Blue Color 0 Register 0x0077,0x00, // LCD Ink/Cursor Green Color 0 Register 0x0078,0x00, // LCD Ink/Cursor Red Color 0 Register 0x007a,0x1f, // LCD Ink/Cursor Blue Color 1 Register 0x007b,0x3f, // LCD Ink/Cursor Green Color 1 Register 0x007c,0x1f, // LCD Ink/Cursor Red Color 1 Register 0x007e,0x00, // LCD Ink/Cursor FIFO Threshold Register 0x0080,0x00, // CRT/TV Ink/Cursor Control Register 0x0081,0x01, // CRT/TV Ink/Cursor Start Address Register 0x0082,0x00, // CRT/TV Cursor X Position Register 0 0x0083,0x00, // CRT/TV Cursor X Position Register 1 0x0084,0x00, // CRT/TV Cursor Y Position Register 0 0x0085,0x00, // CRT/TV Cursor Y Position Register 1 0x0086,0x00, // CRT/TV Ink/Cursor Blue Color 0 Register 0x0087,0x00, // CRT/TV Ink/Cursor Green Color 0 Register 0x0088,0x00, // CRT/TV Ink/Cursor Red Color 0 Register 0x008a,0x1f, // CRT/TV Ink/Cursor Blue Color 1 Register 0x008b,0x3f, // CRT/TV Ink/Cursor Green Color 1 Register 0x008c,0x1f, // CRT/TV Ink/Cursor Red Color 1 Register 0x008e,0x00, // CRT/TV Ink/Cursor FIFO Threshold Register 0x0100,0x00, // BitBlt Control Register 0 0x0101,0x00, // BitBlt Control Register 1 0x0102,0x00, // BitBlt ROP Code/Color Expansion Register 0x0103,0x00, // BitBlt Operation Register 0x0104,0x00, // BitBlt Source Start Address Register 0 0x0105,0x00, // BitBlt Source Start Address Register 1 0x0106,0x00, // BitBlt Source Start Address Register 2 0x0108,0x00, // BitBlt Destination Start Address Register 0 0x0109,0x00, // BitBlt Destination Start Address Register 1 0x010a,0x00, // BitBlt Destination Start Address Register 2 0x010c,0x00, // BitBlt Memory Address Offset Register 0 0x010d,0x00, // BitBlt Memory Address Offset Register 1 0x0110,0x00, // BitBlt Width Register 0 0x0111,0x00, // BitBlt Width Register 1 0x0112,0x00, // BitBlt Height Register 0 0x0113,0x00, // BitBlt Height Register 1 0x0114,0x00, // BitBlt Background Color Register 0 0x0115,0x00, // BitBlt Background Color Register 1 0x0118,0x00, // BitBlt Foreground Color Register 0 0x0119,0x00, // BitBlt Foreground Color Register 1 0x01e0,0x00, // Look-Up Table Mode Register 0x01e2,0x00, // Look-Up Table Address Register 0x01e4,0x00, // Look-Up Table Data Register 0x01f0,0x00, // Power Save Configuration Register 0x01f1,0x00, // Power Save Status Register 0x01f4,0x00, // CPU-to-Memory Access Watchdog Timer Register Set LDD0. Wait for 100ms. Set this register: 0x01fc,0x01, // Display Mode Register Now set the default contrast, which is 0x36, through the MCU. Set LDD2. Wait for 100ms again. Set the default contrast, which is 0x19, through the MCU. Finally, set LDD1. LDD0, LDD1, and LDD2 is located in the PPC register. 6. Miscellaneous 6.1. Flash memory write enable The Flash Vpp enable is at LDD7 in the PPC register, and it is active high, ie. set it to write. 6.2. RS232 transceiver chip The power to the RS232 transceiver ship for the serial UART is at SA1110 GPIO8, and it is active high, ie. set it to turn it on. Appendix A. References SA1110 manual http://developer.intel.com/design/strong/manuals/27824003.zip SA1111 manual http://developer.intel.com/design/strong/manuals/27824203.pdf Intel SA1110 PocketPC sample code http://developer.intel.com/design/strong/swsup/PPC_BSP1_0_DriverKit.exe Epson controller chip manual http://www.erd.epson.com/vdc/pdf/1356/TM/1356TM.pdf Audio chip data sheet http://www-us.semiconductors.philips.com/acrobat/datasheets/UDA1341TS_1.pdf Appendix B. Windows CE Binary Image Data Format The Windows CE binary image data (.bin) format organizes data by sections. Each section contains a section header that specifies the starting address, length, and checksum for that section. The image terminates with an image record header with the physical address and checksum set to zero. 1. Download file format The following table describes the .bin file format. Field Length (bytes) Description Sync Bytes 7 Byte 0 is B, indicating a binary file format. Bytes 1-6 are reserved and set to 0, 0, 0, F, F, \n Image Header, consisting of: Image Address 4 Physical starting address of image. Image Length 4 Physical length, in bytes, of the image. One or more records, consisting of: Record Address 4 Physical starting address of data record. If zero, this is the end of the file and Record Length contains the starting address of the image. Record Length 4 Length of Record Data, in bytes. Record Checksum 4 Signed 32-byte sum of record data bytes Record Data Record Length Record data 2. Software for debug board Attached is the PPShell program, it's better to install this on Win2000 machine. Make sure that the parallel port is set to EPP mode in the PC BIOS, then you will need to enable the Interrupt in the Windows Control Panel (the exact instruction is in the readme.txt inside the zip file). Next unzip the file and run instppsh2.bat. I have included a test binary image, called boot.bin in the zip file. To flash boot.bin, run ppsh.exe -s boot.bin 3. Writing a new download program The PC program needs to wait for some sync bytes on the parallel port before trying to download the bin file. You have to wait for these bytes: 0xAA, 0x55, 0x55, 0xAA, 0x00, 0x00, 0x09, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0x5A, 0xA5, 0x0A, 0x1A. After getting these bytes, then you start sending the bin file over.