ctu_can_fd_libero_top_syn (synthesis)
Synthesis -
Compiler Report
Compiler Constraint Applicator
Pre-mapping Report
Clock Summary
Mapper Report
Compile Point Summary
Clock Conversion
Timing Report
Performance Summary
Clock Relationships
Interface Information
Detailed Report for Clocks
Clock: SYS_CLK
Starting Points with Worst Slack
Ending Points with Worst Slack
Worst Path Information
DSP Report (09:36 18-čec)
RAM Report (09:36 18-čec)
Fanout Report (09:36 18-čec)
Resource Utilization
Constraint Checker Report (09:35 18-čec)
Hierarchical Area Report(/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/rpt_ctu_can_fd_libero_top) (09:36 18-čec)
Session Log (08:53 18-čec)