#### START OF AREA REPORT #####[
Part: MPF300TFCG1152-1 (Microchip)
Click here to go to specific block report:
ctu_can_fd_libero_top
can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
protocol_control_9_4_true
protocol_control_fsm
dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
dlc_decoder_0
control_counter_9
retransmitt_counter_4
err_detector_true
tx_shift_reg
shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
rx_shift_reg
shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
reintegration_counter
operation_control
fault_confinement
fault_confinement_fsm
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
err_counters
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
fault_confinement_rules
can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0
bit_stuffing
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
bit_destuffing
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_3
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0_0
bus_traffic_counters
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
trigger_mux_2
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_4
dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_1
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_2
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_3
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0
access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0
data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_1
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_2
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_3
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_4
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_5
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_6
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0
test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_1
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_0
rx_buffer_128_true_true_1
rx_buffer_fsm
rx_buffer_pointers_128
rx_buffer_ram_128_true_true
inf_ram_wrapper_32_128_12_true_true
parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_2
txt_buffer_8_5_1_true_true
txt_buffer_ram_5_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7
txt_buffer_fsm_5
txt_buffer_8_7_1_true_true
txt_buffer_ram_7_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_0
txt_buffer_fsm_7
txt_buffer_8_3_1_true_true
txt_buffer_ram_3_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_1
txt_buffer_fsm_3
txt_buffer_8_1_1_true_true
txt_buffer_ram_1_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_2
txt_buffer_fsm_1
txt_buffer_8_4_1_true_true
txt_buffer_ram_4_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_3
txt_buffer_fsm_4
txt_buffer_8_0_1_true_true
txt_buffer_ram_0_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_4
txt_buffer_fsm_0
txt_buffer_8_6_1_true_true
txt_buffer_ram_6_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_5
txt_buffer_fsm_6
txt_buffer_8_2_1_true_true
txt_buffer_ram_2_true_true
inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_6
txt_buffer_fsm_2
tx_arbitrator_8
priority_decoder_8
tx_arbitrator_fsm
frame_filters_true_true_true_true
bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0
bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1
range_filter_29_true
int_manager_12_8
int_module
int_module_0
int_module_1
int_module_2
int_module_3
int_module_4
int_module_5
int_module_6
int_module_7
int_module_8
int_module_9
int_module_10
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
prescaler_8_8_8_5_8_8_8_5_2
bit_time_cfg_capture_8_8_8_5_8_8_8_5
synchronisation_checker
bit_segment_meter_5_8_8_1
bit_time_counters_9_8_1
bit_segment_meter_5_8_8_0
bit_time_counters_9_8_0
segment_end_detector
trigger_generator_2
bit_time_fsm
bus_sampling_255_8_7_8_true_15
sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
trv_delay_measurement_7_8_true_255
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0
data_edge_detector
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
ssp_generator_15
bit_err_detector
sample_mux
tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1
dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1
-------------------------------------------------------------------------------------
######## Utilization report for Top level view: ctu_can_fd_libero_top ########
=====================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 11541 100 %
=================================================
Total SEQUENTIAL ELEMENTS in the block ctu_can_fd_libero_top: 11541 (45.63 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 7010 100 %
ARI1 6234 100 %
=================================================
Total COMBINATIONAL LOGIC in the block ctu_can_fd_libero_top: 13244 (52.37 % Utilization)
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GLOBAL BUFFERS
Name Total elements Utilization Notes
---------------------------------------------------
GLOBAL 2 100 %
===================================================
Total GLOBAL BUFFERS in the block ctu_can_fd_libero_top: 2 (0.01 % Utilization)
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IO PADS
Name Total elements Utilization Notes
-------------------------------------------------
IO 151 100 %
=================================================
Total IO PADS in the block ctu_can_fd_libero_top: 151 (0.60 % Utilization)
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----------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ########
Instance path: ctu_can_fd_libero_top.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
======================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 11541 100 %
=================================================
Total SEQUENTIAL ELEMENTS in the block ctu_can_fd_libero_top.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 11541 (45.63 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 7010 100 %
ARI1 6234 100 %
=================================================
Total COMBINATIONAL LOGIC in the block ctu_can_fd_libero_top.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 13244 (52.37 % Utilization)
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GLOBAL BUFFERS
Name Total elements Utilization Notes
---------------------------------------------------
GLOBAL 1 50 %
===================================================
Total GLOBAL BUFFERS in the block ctu_can_fd_libero_top.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 1 (0.00 % Utilization)
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----------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: bus_sampling_255_8_7_8_true_15 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.bus_sampling_255_8_7_8_true_15
================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 82 0.7110 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.bus_sampling_255_8_7_8_true_15: 82 (0.32 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 64 0.9130 %
ARI1 68 1.09 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.bus_sampling_255_8_7_8_true_15: 132 (0.52 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: bit_err_detector ########
Instance path: bus_sampling_255_8_7_8_true_15.bit_err_detector
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.bit_err_detector: 2 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_sampling_255_8_7_8_true_15.bit_err_detector: 4 (0.02 % Utilization)
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------------------------------------------------------------------------
######## Utilization report for cell: data_edge_detector ########
Instance path: bus_sampling_255_8_7_8_true_15.data_edge_detector
========================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.data_edge_detector: 3 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 3 0.04280 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_sampling_255_8_7_8_true_15.data_edge_detector: 3 (0.01 % Utilization)
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ########
Instance path: bus_sampling_255_8_7_8_true_15.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
==================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1 ########
Instance path: bus_sampling_255_8_7_8_true_15.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1
===================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_sampling_255_8_7_8_true_15.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1: 1 (0.00 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1
==============================================================================================================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1: 1 (0.00 % Utilization)
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----------------------------------------------------------------
######## Utilization report for cell: sample_mux ########
Instance path: bus_sampling_255_8_7_8_true_15.sample_mux
================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.sample_mux: 1 (0.00 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_sampling_255_8_7_8_true_15.sample_mux: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: bus_sampling_255_8_7_8_true_15.sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 2 (0.01 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: ssp_generator_15 ########
Instance path: bus_sampling_255_8_7_8_true_15.ssp_generator_15
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 33 0.2860 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.ssp_generator_15: 33 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 16 0.2280 %
ARI1 47 0.7540 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_sampling_255_8_7_8_true_15.ssp_generator_15: 63 (0.25 % Utilization)
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----------------------------------------------------------------------------------------
######## Utilization report for cell: trv_delay_measurement_7_8_true_255 ########
Instance path: bus_sampling_255_8_7_8_true_15.trv_delay_measurement_7_8_true_255
========================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 25 0.2170 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.trv_delay_measurement_7_8_true_255: 25 (0.10 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 23 0.3280 %
ARI1 16 0.2570 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_sampling_255_8_7_8_true_15.trv_delay_measurement_7_8_true_255: 39 (0.15 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0 ########
Instance path: trv_delay_measurement_7_8_true_255.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0
===================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block trv_delay_measurement_7_8_true_255.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0: 1 (0.00 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0
==============================================================================================================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0: 1 (0.00 % Utilization)
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######## Utilization report for cell: tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: bus_sampling_255_8_7_8_true_15.tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
====================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 14 0.1210 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_sampling_255_8_7_8_true_15.tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 14 (0.06 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 14 0.20 %
ARI1 5 0.08020 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_sampling_255_8_7_8_true_15.tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 19 (0.08 % Utilization)
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-------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===========================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 425 3.68 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 425 (1.68 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1008 14.4 %
ARI1 175 2.81 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1183 (4.68 % Utilization)
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-----------------------------------------------------------------------------------------
######## Utilization report for cell: bit_destuffing ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bit_destuffing
=========================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 12 0.1040 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bit_destuffing: 12 (0.05 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 19 0.2710 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bit_destuffing: 19 (0.08 % Utilization)
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######## Utilization report for cell: dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0 ########
Instance path: bit_destuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
====================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_destuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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--------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0_0 ########
Instance path: bit_destuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0_0
====================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_destuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0_0: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1 ########
Instance path: bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
=============================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2 ########
Instance path: bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2
=============================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_3 ########
Instance path: bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_3
=============================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_3: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ########
Instance path: bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
===============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_destuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------------------
######## Utilization report for cell: bit_stuffing ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bit_stuffing
=======================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 10 0.08660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bit_stuffing: 10 (0.04 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 21 0.30 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bit_stuffing: 21 (0.08 % Utilization)
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------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: bit_stuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
==================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_stuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ########
Instance path: bit_stuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
==================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_stuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 2 0.02850 %
=================================================
Total COMBINATIONAL LOGIC in the block bit_stuffing.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 2 (0.01 % Utilization)
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: bit_stuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===========================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_stuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0 ########
Instance path: bit_stuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
=============================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bit_stuffing.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------
######## Utilization report for cell: bus_traffic_counters ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bus_traffic_counters
===============================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 68 0.5890 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bus_traffic_counters: 68 (0.27 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 3 0.04280 %
ARI1 32 0.5130 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.bus_traffic_counters: 35 (0.14 % Utilization)
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--------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: bus_traffic_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
==============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_traffic_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_traffic_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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----------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2 ########
Instance path: bus_traffic_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2
================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block bus_traffic_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block bus_traffic_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
=======================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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######## Utilization report for cell: can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 53 0.4590 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 53 (0.21 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 70 0.9990 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 70 (0.28 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 15 0.130 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 15 (0.06 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 17 0.2430 %
=================================================
Total COMBINATIONAL LOGIC in the block can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 17 (0.07 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ########
Instance path: can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
===================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 17 0.1470 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 17 (0.07 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 21 0.30 %
=================================================
Total COMBINATIONAL LOGIC in the block can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 21 (0.08 % Utilization)
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######## Utilization report for cell: crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 ########
Instance path: can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0
===================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 21 0.1820 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0: 21 (0.08 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 25 0.3570 %
=================================================
Total COMBINATIONAL LOGIC in the block can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0: 25 (0.10 % Utilization)
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--------------------------------------------------------------------------------------------
######## Utilization report for cell: fault_confinement ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.fault_confinement
============================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 55 0.4770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.fault_confinement: 55 (0.22 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 62 0.8840 %
ARI1 87 1.4 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.fault_confinement: 149 (0.59 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: err_counters ########
Instance path: fault_confinement.err_counters
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 51 0.4420 %
=================================================
Total SEQUENTIAL ELEMENTS in the block fault_confinement.err_counters: 51 (0.20 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 46 0.6560 %
ARI1 51 0.8180 %
=================================================
Total COMBINATIONAL LOGIC in the block fault_confinement.err_counters: 97 (0.38 % Utilization)
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0 ########
Instance path: err_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
============================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block err_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block err_counters.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
================================================================================================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------
######## Utilization report for cell: fault_confinement_fsm ########
Instance path: fault_confinement.fault_confinement_fsm
===========================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 4 0.03470 %
=================================================
Total SEQUENTIAL ELEMENTS in the block fault_confinement.fault_confinement_fsm: 4 (0.02 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 9 0.1280 %
ARI1 36 0.5770 %
=================================================
Total COMBINATIONAL LOGIC in the block fault_confinement.fault_confinement_fsm: 45 (0.18 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0 ########
Instance path: fault_confinement_fsm.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
==============================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block fault_confinement_fsm.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------
######## Utilization report for cell: fault_confinement_rules ########
Instance path: fault_confinement.fault_confinement_rules
=============================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 7 0.09990 %
=================================================
Total COMBINATIONAL LOGIC in the block fault_confinement.fault_confinement_rules: 7 (0.03 % Utilization)
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--------------------------------------------------------------------------------------------
######## Utilization report for cell: operation_control ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.operation_control
============================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.operation_control: 2 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 11 0.1570 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.operation_control: 11 (0.04 % Utilization)
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----------------------------------------------------------------------------------------------------
######## Utilization report for cell: protocol_control_9_4_true ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.protocol_control_9_4_true
====================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 223 1.93 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.protocol_control_9_4_true: 223 (0.88 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 819 11.7 %
ARI1 56 0.8980 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.protocol_control_9_4_true: 875 (3.46 % Utilization)
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-----------------------------------------------------------------------
######## Utilization report for cell: control_counter_9 ########
Instance path: protocol_control_9_4_true.control_counter_9
=======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 26 0.2250 %
=================================================
Total SEQUENTIAL ELEMENTS in the block protocol_control_9_4_true.control_counter_9: 26 (0.10 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 31 0.4420 %
ARI1 18 0.2890 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_9_4_true.control_counter_9: 49 (0.19 % Utilization)
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-----------------------------------------------------------------------
######## Utilization report for cell: err_detector_true ########
Instance path: protocol_control_9_4_true.err_detector_true
=======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 10 0.08660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block protocol_control_9_4_true.err_detector_true: 10 (0.04 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 20 0.2850 %
ARI1 28 0.4490 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_9_4_true.err_detector_true: 48 (0.19 % Utilization)
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--------------------------------------------------------------------------
######## Utilization report for cell: protocol_control_fsm ########
Instance path: protocol_control_9_4_true.protocol_control_fsm
==========================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 67 0.5810 %
=================================================
Total SEQUENTIAL ELEMENTS in the block protocol_control_9_4_true.protocol_control_fsm: 67 (0.26 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 537 7.66 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_9_4_true.protocol_control_fsm: 537 (2.12 % Utilization)
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-------------------------------------------------------------------
######## Utilization report for cell: dlc_decoder_0 ########
Instance path: protocol_control_fsm.dlc_decoder_0
===================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 7 0.09990 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_fsm.dlc_decoder_0: 7 (0.03 % Utilization)
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---------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: protocol_control_fsm.dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===========================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 10 0.1430 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_fsm.dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 10 (0.04 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0 ########
Instance path: protocol_control_fsm.dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
=============================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_fsm.dlc_decoder_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------
######## Utilization report for cell: reintegration_counter ########
Instance path: protocol_control_9_4_true.reintegration_counter
===========================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 9 0.0780 %
=================================================
Total SEQUENTIAL ELEMENTS in the block protocol_control_9_4_true.reintegration_counter: 9 (0.04 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
ARI1 10 0.160 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_9_4_true.reintegration_counter: 14 (0.06 % Utilization)
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---------------------------------------------------------------------------
######## Utilization report for cell: retransmitt_counter_4 ########
Instance path: protocol_control_9_4_true.retransmitt_counter_4
===========================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 4 0.03470 %
=================================================
Total SEQUENTIAL ELEMENTS in the block protocol_control_9_4_true.retransmitt_counter_4: 4 (0.02 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 6 0.08560 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_9_4_true.retransmitt_counter_4: 6 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: rx_shift_reg ########
Instance path: protocol_control_9_4_true.rx_shift_reg
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 75 0.650 %
=================================================
Total SEQUENTIAL ELEMENTS in the block protocol_control_9_4_true.rx_shift_reg: 75 (0.30 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 10 0.1430 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_9_4_true.rx_shift_reg: 10 (0.04 % Utilization)
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: rx_shift_reg.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
==========================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rx_shift_reg.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_shift_reg.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
============================================================================================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: rx_shift_reg.shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
=====================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 32 0.2770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rx_shift_reg.shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 32 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 3 0.04280 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_shift_reg.shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 3 (0.01 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: tx_shift_reg ########
Instance path: protocol_control_9_4_true.tx_shift_reg
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 32 0.2770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block protocol_control_9_4_true.tx_shift_reg: 32 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 211 3.01 %
=================================================
Total COMBINATIONAL LOGIC in the block protocol_control_9_4_true.tx_shift_reg: 211 (0.83 % Utilization)
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------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: tx_shift_reg.shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
========================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 32 0.2770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block tx_shift_reg.shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 32 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 90 1.28 %
=================================================
Total COMBINATIONAL LOGIC in the block tx_shift_reg.shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 90 (0.36 % Utilization)
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----------------------------------------------------------------------------------------
######## Utilization report for cell: trigger_mux_2 ########
Instance path: can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.trigger_mux_2
========================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.trigger_mux_2: 2 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 3 0.04280 %
=================================================
Total COMBINATIONAL LOGIC in the block can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.trigger_mux_2: 3 (0.01 % Utilization)
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--------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1 ########
Instance path: trigger_mux_2.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
====================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block trigger_mux_2.dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_4 ########
Instance path: trigger_mux_2.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_4
=============================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block trigger_mux_2.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_4: 1 (0.00 % Utilization)
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-------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: frame_filters_true_true_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.frame_filters_true_true_true_true
===================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.frame_filters_true_true_true_true: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 58 0.8270 %
ARI1 103 1.65 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.frame_filters_true_true_true_true: 161 (0.64 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ########
Instance path: frame_filters_true_true_true_true.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
=========================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 14 0.20 %
ARI1 15 0.2410 %
=================================================
Total COMBINATIONAL LOGIC in the block frame_filters_true_true_true_true.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 29 (0.11 % Utilization)
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-------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0 ########
Instance path: frame_filters_true_true_true_true.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0
===========================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 14 0.20 %
ARI1 15 0.2410 %
=================================================
Total COMBINATIONAL LOGIC in the block frame_filters_true_true_true_true.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_0: 29 (0.11 % Utilization)
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-------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1 ########
Instance path: frame_filters_true_true_true_true.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1
===========================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 15 0.2140 %
ARI1 15 0.2410 %
=================================================
Total COMBINATIONAL LOGIC in the block frame_filters_true_true_true_true.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_1: 30 (0.12 % Utilization)
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--------------------------------------------------------------------------
######## Utilization report for cell: range_filter_29_true ########
Instance path: frame_filters_true_true_true_true.range_filter_29_true
==========================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
ARI1 58 0.930 %
=================================================
Total COMBINATIONAL LOGIC in the block frame_filters_true_true_true_true.range_filter_29_true: 59 (0.23 % Utilization)
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--------------------------------------------------------------------------------------------------
######## Utilization report for cell: int_manager_12_8 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.int_manager_12_8
==================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 37 0.3210 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.int_manager_12_8: 37 (0.15 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 69 0.9840 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.int_manager_12_8: 69 (0.27 % Utilization)
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-----------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1 ########
Instance path: int_manager_12_8.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
=================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1: 1 (0.00 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1: 1 (0.00 % Utilization)
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----------------------------------------------------------------
######## Utilization report for cell: int_module ########
Instance path: int_manager_12_8.int_module
================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module: 3 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_0 ########
Instance path: int_manager_12_8.int_module_0
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_0: 3 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_0: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_1 ########
Instance path: int_manager_12_8.int_module_1
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_1: 3 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 2 0.02850 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_1: 2 (0.01 % Utilization)
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-------------------------------------------------------------------
######## Utilization report for cell: int_module_10 ########
Instance path: int_manager_12_8.int_module_10
===================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_10: 3 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_10: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_2 ########
Instance path: int_manager_12_8.int_module_2
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_2: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_2: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_3 ########
Instance path: int_manager_12_8.int_module_3
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_3: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_3: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_4 ########
Instance path: int_manager_12_8.int_module_4
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_4: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_4: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_5 ########
Instance path: int_manager_12_8.int_module_5
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_5: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_5: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_6 ########
Instance path: int_manager_12_8.int_module_6
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_6: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_6: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_7 ########
Instance path: int_manager_12_8.int_module_7
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_7: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_7: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_8 ########
Instance path: int_manager_12_8.int_module_8
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_8: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_8: 4 (0.02 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: int_module_9 ########
Instance path: int_manager_12_8.int_module_9
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 3 0.0260 %
=================================================
Total SEQUENTIAL ELEMENTS in the block int_manager_12_8.int_module_9: 3 (0.01 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block int_manager_12_8.int_module_9: 4 (0.02 % Utilization)
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---------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 536 4.64 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 536 (2.12 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1159 16.5 %
ARI1 139 2.23 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1298 (5.13 % Utilization)
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GLOBAL BUFFERS
Name Total elements Utilization Notes
---------------------------------------------------
GLOBAL 1 50 %
===================================================
Total GLOBAL BUFFERS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
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-------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
=============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 436 3.78 %
=================================================
Total SEQUENTIAL ELEMENTS in the block memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 436 (1.72 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 745 10.6 %
ARI1 117 1.88 %
=================================================
Total COMBINATIONAL LOGIC in the block memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 862 (3.41 % Utilization)
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-------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
=============================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 4 (0.02 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
============================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 5 (0.02 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
=====================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 32 0.2770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 32 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 600 8.56 %
ARI1 113 1.81 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 713 (2.82 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0: 8 (0.03 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 2 0.02850 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0: 2 (0.01 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 9 0.0780 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0: 9 (0.04 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 6 0.08560 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0: 6 (0.02 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0: 29 (0.11 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0: 5 (0.02 % Utilization)
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----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_0
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_0: 29 (0.11 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_0: 4 (0.02 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_1 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_1
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_1: 29 (0.11 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_1: 5 (0.02 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_2 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_2
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_2: 29 (0.11 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_2: 4 (0.02 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_3 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_3
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_3: 29 (0.11 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_3: 5 (0.02 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_4 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_4
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_4: 29 (0.11 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_4: 5 (0.02 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_5 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_5
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_5: 29 (0.11 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_5: 5 (0.02 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_6 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_6
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_6: 29 (0.11 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0_6: 5 (0.02 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 16 0.1390 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0: 16 (0.06 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 3 0.04280 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0: 3 (0.01 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0: 1 (0.00 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 2 0.02850 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0: 2 (0.01 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 9 0.0780 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0: 9 (0.04 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 8 0.1140 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0: 8 (0.03 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 24 0.2080 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0: 24 (0.09 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0: 4 (0.02 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0
========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 10 0.08660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0: 10 (0.04 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0: 4 (0.02 % Utilization)
Top
-------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0
=======================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 14 0.1210 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0: 14 (0.06 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0: 5 (0.02 % Utilization)
Top
-------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0
=======================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 12 0.1040 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0: 12 (0.05 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 3 0.04280 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0: 3 (0.01 % Utilization)
Top
-------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0
=======================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 10 0.1430 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0: 10 (0.04 % Utilization)
Top
-------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0
=======================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 34 0.4850 %
ARI1 4 0.06420 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0: 38 (0.15 % Utilization)
Top
---------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_0
=========================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_0: 1 (0.00 % Utilization)
Top
---------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_1 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_1
=========================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_1: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_2 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_2
=========================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_2: 1 (0.00 % Utilization)
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---------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_3 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_3
=========================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0_3: 1 (0.00 % Utilization)
Top
-------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0
=======================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 32 0.2770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0: 32 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 6 0.08560 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0: 6 (0.02 % Utilization)
Top
-------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0
=======================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 29 0.2510 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0: 29 (0.11 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 5 0.07130 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0: 5 (0.02 % Utilization)
Top
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######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0 ########
Instance path: control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0
=======================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0: 1 (0.00 % Utilization)
Top
---------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0 ########
Instance path: memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0
=============================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 2 (0.01 % Utilization)
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GLOBAL BUFFERS
Name Total elements Utilization Notes
---------------------------------------------------
GLOBAL 1 50 %
===================================================
Total GLOBAL BUFFERS in the block memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0: 1 (0.00 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_1 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_1
=========================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_1: 2 (0.01 % Utilization)
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GLOBAL BUFFERS
Name Total elements Utilization Notes
---------------------------------------------------
GLOBAL 1 50 %
===================================================
Total GLOBAL BUFFERS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_1: 1 (0.00 % Utilization)
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######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1 ########
Instance path: memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1
=============================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1: 1 (0.00 % Utilization)
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######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_0 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_0
=========================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_9_0: 1 (0.00 % Utilization)
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----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 86 0.7450 %
=================================================
Total SEQUENTIAL ELEMENTS in the block memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 86 (0.34 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 85 1.21 %
ARI1 4 0.06420 %
=================================================
Total COMBINATIONAL LOGIC in the block memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 89 (0.35 % Utilization)
Top
--------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
==================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 32 0.2770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 32 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 67 0.9560 %
ARI1 4 0.06420 %
=================================================
Total COMBINATIONAL LOGIC in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 71 (0.28 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
====================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 1 (0.00 % Utilization)
Top
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
=================================================
Total COMBINATIONAL LOGIC in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 4 (0.02 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ########
Instance path: test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0
====================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 21 0.1820 %
=================================================
Total SEQUENTIAL ELEMENTS in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 21 (0.08 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 7 0.09990 %
=================================================
Total COMBINATIONAL LOGIC in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0: 7 (0.03 % Utilization)
Top
----------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 ########
Instance path: test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0
====================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 32 0.2770 %
=================================================
Total SEQUENTIAL ELEMENTS in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0: 32 (0.13 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 6 0.08560 %
=================================================
Total COMBINATIONAL LOGIC in the block test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0: 6 (0.02 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_2 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_2
=======================================================================================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 11 0.1570 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_2: 11 (0.04 % Utilization)
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-------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: prescaler_8_8_8_5_8_8_8_5_2 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.prescaler_8_8_8_5_8_8_8_5_2
=============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 80 0.6930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.prescaler_8_8_8_5_8_8_8_5_2: 80 (0.32 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 207 2.95 %
ARI1 191 3.06 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.prescaler_8_8_8_5_8_8_8_5_2: 398 (1.57 % Utilization)
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-------------------------------------------------------------------------------
######## Utilization report for cell: bit_segment_meter_5_8_8_0 ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.bit_segment_meter_5_8_8_0
===============================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 10 0.08660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.bit_segment_meter_5_8_8_0: 10 (0.04 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 39 0.5560 %
ARI1 71 1.14 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.bit_segment_meter_5_8_8_0: 110 (0.43 % Utilization)
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-------------------------------------------------------------------------------
######## Utilization report for cell: bit_segment_meter_5_8_8_1 ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.bit_segment_meter_5_8_8_1
===============================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 10 0.08660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.bit_segment_meter_5_8_8_1: 10 (0.04 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 40 0.5710 %
ARI1 73 1.17 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.bit_segment_meter_5_8_8_1: 113 (0.45 % Utilization)
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------------------------------------------------------------------------------------------
######## Utilization report for cell: bit_time_cfg_capture_8_8_8_5_8_8_8_5 ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.bit_time_cfg_capture_8_8_8_5_8_8_8_5
==========================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 17 0.1470 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_cfg_capture_8_8_8_5_8_8_8_5: 17 (0.07 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 4 0.05710 %
ARI1 13 0.2090 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_cfg_capture_8_8_8_5_8_8_8_5: 17 (0.07 % Utilization)
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-----------------------------------------------------------------------------
######## Utilization report for cell: bit_time_counters_9_8_0 ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.bit_time_counters_9_8_0
=============================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 17 0.1470 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_counters_9_8_0: 17 (0.07 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 36 0.5140 %
ARI1 17 0.2730 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_counters_9_8_0: 53 (0.21 % Utilization)
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-----------------------------------------------------------------------------
######## Utilization report for cell: bit_time_counters_9_8_1 ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.bit_time_counters_9_8_1
=============================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 17 0.1470 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_counters_9_8_1: 17 (0.07 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 34 0.4850 %
ARI1 17 0.2730 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_counters_9_8_1: 51 (0.20 % Utilization)
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------------------------------------------------------------------
######## Utilization report for cell: bit_time_fsm ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.bit_time_fsm
==================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 4 0.03470 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_fsm: 4 (0.02 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 7 0.09990 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.bit_time_fsm: 7 (0.03 % Utilization)
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--------------------------------------------------------------------------
######## Utilization report for cell: segment_end_detector ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.segment_end_detector
==========================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.segment_end_detector: 2 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 36 0.5140 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.segment_end_detector: 36 (0.14 % Utilization)
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-----------------------------------------------------------------------------
######## Utilization report for cell: synchronisation_checker ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.synchronisation_checker
=============================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.synchronisation_checker: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 8 0.1140 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.synchronisation_checker: 8 (0.03 % Utilization)
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-------------------------------------------------------------------------
######## Utilization report for cell: trigger_generator_2 ########
Instance path: prescaler_8_8_8_5_8_8_8_5_2.trigger_generator_2
=========================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block prescaler_8_8_8_5_8_8_8_5_2.trigger_generator_2: 2 (0.01 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 3 0.04280 %
=================================================
Total COMBINATIONAL LOGIC in the block prescaler_8_8_8_5_8_8_8_5_2.trigger_generator_2: 3 (0.01 % Utilization)
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-------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0
===========================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 2 0.01730 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0: 2 (0.01 % Utilization)
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-----------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rx_buffer_128_true_true_1 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.rx_buffer_128_true_true_1
===========================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 4390 38 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.rx_buffer_128_true_true_1: 4390 (17.36 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 970 13.8 %
ARI1 2654 42.6 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.rx_buffer_128_true_true_1: 3624 (14.33 % Utilization)
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ########
Instance path: rx_buffer_128_true_true_1.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
=================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rx_buffer_128_true_true_1.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_buffer_128_true_true_1.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 1 (0.00 % Utilization)
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ########
Instance path: rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
==========================================================================================================================================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 1 0.008660 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 1 (0.00 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 1 0.01430 %
=================================================
Total COMBINATIONAL LOGIC in the block rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_10_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 1 (0.00 % Utilization)
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-------------------------------------------------------------------
######## Utilization report for cell: rx_buffer_fsm ########
Instance path: rx_buffer_128_true_true_1.rx_buffer_fsm
===================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rx_buffer_128_true_true_1.rx_buffer_fsm: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 16 0.2280 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_buffer_128_true_true_1.rx_buffer_fsm: 16 (0.06 % Utilization)
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----------------------------------------------------------------------------
######## Utilization report for cell: rx_buffer_pointers_128 ########
Instance path: rx_buffer_128_true_true_1.rx_buffer_pointers_128
============================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 44 0.3810 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rx_buffer_128_true_true_1.rx_buffer_pointers_128: 44 (0.17 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 45 0.6420 %
ARI1 40 0.6420 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_buffer_128_true_true_1.rx_buffer_pointers_128: 85 (0.34 % Utilization)
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---------------------------------------------------------------------------------
######## Utilization report for cell: rx_buffer_ram_128_true_true ########
Instance path: rx_buffer_128_true_true_1.rx_buffer_ram_128_true_true
=================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 4257 36.9 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rx_buffer_128_true_true_1.rx_buffer_ram_128_true_true: 4257 (16.83 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 731 10.4 %
ARI1 2608 41.8 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_buffer_128_true_true_1.rx_buffer_ram_128_true_true: 3339 (13.20 % Utilization)
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-----------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_128_12_true_true ########
Instance path: rx_buffer_ram_128_true_true.inf_ram_wrapper_32_128_12_true_true
=========================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 4128 35.8 %
=================================================
Total SEQUENTIAL ELEMENTS in the block rx_buffer_ram_128_true_true.inf_ram_wrapper_32_128_12_true_true: 4128 (16.32 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 505 7.2 %
ARI1 2518 40.4 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_buffer_ram_128_true_true.inf_ram_wrapper_32_128_12_true_true: 3023 (11.95 % Utilization)
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ########
Instance path: rx_buffer_ram_128_true_true.parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
=========================================================================================================================================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 13 0.1850 %
=================================================
Total COMBINATIONAL LOGIC in the block rx_buffer_ram_128_true_true.parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1: 13 (0.05 % Utilization)
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-------------------------------------------------------------------------------------------------
######## Utilization report for cell: tx_arbitrator_8 ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.tx_arbitrator_8
=================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 116 1.01 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.tx_arbitrator_8: 116 (0.46 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 177 2.52 %
ARI1 248 3.98 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.tx_arbitrator_8: 425 (1.68 % Utilization)
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------------------------------------------------------------------------
######## Utilization report for cell: priority_decoder_8 ########
Instance path: tx_arbitrator_8.priority_decoder_8
========================================================================
COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 71 1.01 %
ARI1 6 0.09620 %
=================================================
Total COMBINATIONAL LOGIC in the block tx_arbitrator_8.priority_decoder_8: 77 (0.30 % Utilization)
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-----------------------------------------------------------------------
######## Utilization report for cell: tx_arbitrator_fsm ########
Instance path: tx_arbitrator_8.tx_arbitrator_fsm
=======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 9 0.0780 %
=================================================
Total SEQUENTIAL ELEMENTS in the block tx_arbitrator_8.tx_arbitrator_fsm: 9 (0.04 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 47 0.670 %
=================================================
Total COMBINATIONAL LOGIC in the block tx_arbitrator_8.tx_arbitrator_fsm: 47 (0.19 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_0_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_0_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_0_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 439 6.26 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_0_1_true_true: 771 (3.05 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_0 ########
Instance path: txt_buffer_8_0_1_true_true.txt_buffer_fsm_0
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_0_1_true_true.txt_buffer_fsm_0: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 47 0.670 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_0_1_true_true.txt_buffer_fsm_0: 47 (0.19 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_0_true_true ########
Instance path: txt_buffer_8_0_1_true_true.txt_buffer_ram_0_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_0_1_true_true.txt_buffer_ram_0_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 358 5.11 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_0_1_true_true.txt_buffer_ram_0_true_true: 690 (2.73 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_4 ########
Instance path: txt_buffer_ram_0_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_4
============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_0_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_4: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_0_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_4: 570 (2.25 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_1_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_1_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_1_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 408 5.82 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_1_1_true_true: 740 (2.93 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_1 ########
Instance path: txt_buffer_8_1_1_true_true.txt_buffer_fsm_1
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_1_1_true_true.txt_buffer_fsm_1: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 43 0.6130 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_1_1_true_true.txt_buffer_fsm_1: 43 (0.17 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_1_true_true ########
Instance path: txt_buffer_8_1_1_true_true.txt_buffer_ram_1_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_1_1_true_true.txt_buffer_ram_1_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 330 4.71 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_1_1_true_true.txt_buffer_ram_1_true_true: 662 (2.62 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_2 ########
Instance path: txt_buffer_ram_1_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_2
============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_1_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_2: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_1_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_2: 570 (2.25 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_2_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_2_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_2_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 402 5.73 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_2_1_true_true: 734 (2.90 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_2 ########
Instance path: txt_buffer_8_2_1_true_true.txt_buffer_fsm_2
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_2_1_true_true.txt_buffer_fsm_2: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 40 0.5710 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_2_1_true_true.txt_buffer_fsm_2: 40 (0.16 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_2_true_true ########
Instance path: txt_buffer_8_2_1_true_true.txt_buffer_ram_2_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_2_1_true_true.txt_buffer_ram_2_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 329 4.69 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_2_1_true_true.txt_buffer_ram_2_true_true: 661 (2.61 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_6 ########
Instance path: txt_buffer_ram_2_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_6
============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_2_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_6: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_2_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_6: 570 (2.25 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_3_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_3_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_3_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 405 5.78 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_3_1_true_true: 737 (2.91 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_3 ########
Instance path: txt_buffer_8_3_1_true_true.txt_buffer_fsm_3
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_3_1_true_true.txt_buffer_fsm_3: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 40 0.5710 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_3_1_true_true.txt_buffer_fsm_3: 40 (0.16 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_3_true_true ########
Instance path: txt_buffer_8_3_1_true_true.txt_buffer_ram_3_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_3_1_true_true.txt_buffer_ram_3_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 329 4.69 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_3_1_true_true.txt_buffer_ram_3_true_true: 661 (2.61 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_1 ########
Instance path: txt_buffer_ram_3_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_1
============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_3_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_1: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_3_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_1: 570 (2.25 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_4_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_4_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_4_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 408 5.82 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_4_1_true_true: 740 (2.93 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_4 ########
Instance path: txt_buffer_8_4_1_true_true.txt_buffer_fsm_4
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_4_1_true_true.txt_buffer_fsm_4: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 45 0.6420 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_4_1_true_true.txt_buffer_fsm_4: 45 (0.18 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_4_true_true ########
Instance path: txt_buffer_8_4_1_true_true.txt_buffer_ram_4_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_4_1_true_true.txt_buffer_ram_4_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 330 4.71 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_4_1_true_true.txt_buffer_ram_4_true_true: 662 (2.62 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_3 ########
Instance path: txt_buffer_ram_4_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_3
============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_4_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_3: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_4_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_3: 570 (2.25 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_5_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_5_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_5_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 409 5.83 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_5_1_true_true: 741 (2.93 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_5 ########
Instance path: txt_buffer_8_5_1_true_true.txt_buffer_fsm_5
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_5_1_true_true.txt_buffer_fsm_5: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 44 0.6280 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_5_1_true_true.txt_buffer_fsm_5: 44 (0.17 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_5_true_true ########
Instance path: txt_buffer_8_5_1_true_true.txt_buffer_ram_5_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_5_1_true_true.txt_buffer_ram_5_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 329 4.69 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_5_1_true_true.txt_buffer_ram_5_true_true: 661 (2.61 % Utilization)
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----------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7 ########
Instance path: txt_buffer_ram_5_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7
==========================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_5_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_5_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7: 570 (2.25 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_6_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_6_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_6_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 407 5.81 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_6_1_true_true: 739 (2.92 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_6 ########
Instance path: txt_buffer_8_6_1_true_true.txt_buffer_fsm_6
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_6_1_true_true.txt_buffer_fsm_6: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 42 0.5990 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_6_1_true_true.txt_buffer_fsm_6: 42 (0.17 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_6_true_true ########
Instance path: txt_buffer_8_6_1_true_true.txt_buffer_ram_6_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_6_1_true_true.txt_buffer_ram_6_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 329 4.69 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_6_1_true_true.txt_buffer_ram_6_true_true: 661 (2.61 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_5 ########
Instance path: txt_buffer_ram_6_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_5
============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_6_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_5: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_6_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_5: 570 (2.25 % Utilization)
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------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_8_7_1_true_true ########
Instance path: can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_7_1_true_true
============================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 734 6.36 %
=================================================
Total SEQUENTIAL ELEMENTS in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_7_1_true_true: 734 (2.90 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 409 5.83 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.txt_buffer_8_7_1_true_true: 741 (2.93 % Utilization)
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----------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_fsm_7 ########
Instance path: txt_buffer_8_7_1_true_true.txt_buffer_fsm_7
======================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 8 0.06930 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_7_1_true_true.txt_buffer_fsm_7: 8 (0.03 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 44 0.6280 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_7_1_true_true.txt_buffer_fsm_7: 44 (0.17 % Utilization)
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--------------------------------------------------------------------------------
######## Utilization report for cell: txt_buffer_ram_7_true_true ########
Instance path: txt_buffer_8_7_1_true_true.txt_buffer_ram_7_true_true
================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 726 6.29 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_8_7_1_true_true.txt_buffer_ram_7_true_true: 726 (2.87 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 329 4.69 %
ARI1 332 5.33 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_8_7_1_true_true.txt_buffer_ram_7_true_true: 661 (2.61 % Utilization)
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------------------------------------------------------------------------------------------------------------------------------------------------------------
######## Utilization report for cell: inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_0 ########
Instance path: txt_buffer_ram_7_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_0
============================================================================================================================================================
SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
-------------------------------------------------
SLE 704 6.1 %
=================================================
Total SEQUENTIAL ELEMENTS in the block txt_buffer_ram_7_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_0: 704 (2.78 % Utilization)
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COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-------------------------------------------------
CFG 250 3.57 %
ARI1 320 5.13 %
=================================================
Total COMBINATIONAL LOGIC in the block txt_buffer_ram_7_true_true.inf_ram_wrapper_32_21_5_true_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_7_0: 570 (2.25 % Utilization)
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##### END OF AREA REPORT #####]