#Build: Synplify Pro (R) S-2021.09M, Build 223R, Feb 23 2022 #install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro #OS: Linux #Hostname: ondrej-Aspire-V3-771 # Mon Jul 18 09:34:51 2022 #Implementation: synthesis Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: S-2021.09M Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro OS: Ubuntu 20.04.4 LTS Hostname: ondrej-Aspire-V3-771 max virtual memory: unlimited (bytes) max user processes: 63079 max stack size: 8388608 (bytes) Implementation : synthesis Synopsys HDL Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: S-2021.09M Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro OS: Ubuntu 20.04.4 LTS Hostname: ondrej-Aspire-V3-771 max virtual memory: unlimited (bytes) max user processes: 63079 max stack size: 8388608 (bytes) Implementation : synthesis Synopsys VHDL Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246 @N: : | Running in 64-bit mode @N: : | stack limit increased to max @N: : ctu_can_fd_libero_top.vhd(90) | Top entity is set to ctu_can_fd_libero_top. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst_ce.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_constants_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_frame_format.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_register_map.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_config_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/drv_stat_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/unary_ops_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/mux2.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_byte.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_preload.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sig_sync.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/access_signaler.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/address_decoder.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_mux.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_registers_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/cmn_reg_map_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/parity_calculator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_sync.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_types_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/id_transfer_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_destuffing.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_stuffing.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_traffic_counters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/crc_calc.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_counters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_rules.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/endian_swapper.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dlc_decoder.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/reintegration_counter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/retransmitt_counter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_shift_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_shift_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_mux.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_err_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_edge_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trv_delay_meas.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sample_mux.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_module.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/clk_gate.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/priority_decoder.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_filter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/range_filter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_segment_meter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_generator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/synchronisation_checker.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/prescaler.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ctu_can_fd_libero_top.vhd'. VHDL syntax check successful! @N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000". @N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time. At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB) Process completed successfully. # Mon Jul 18 09:34:52 2022 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: S-2021.09M Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro OS: Ubuntu 20.04.4 LTS Hostname: ondrej-Aspire-V3-771 max virtual memory: unlimited (bytes) max user processes: 63079 max stack size: 8388608 (bytes) Implementation : synthesis Synopsys Verilog Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246 @N: : | Running in 64-bit mode @I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/generic/acg5.v" (library work) @I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__) @I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps) @I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps) @I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps) @I::"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v" (library work) @W:CG100 : polarfire_syn_comps.v(21) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(61) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(88) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(118) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(168) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(213) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(232) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(281) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(335) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(657) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(761) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(795) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1059) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1369) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1396) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1441) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1474) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1492) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1518) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1559) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1581) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1599) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1616) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1635) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1652) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1681) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1712) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1802) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2026) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2187) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2203) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2219) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2235) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2267) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2648) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3661) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3732) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3861) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3879) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3896) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3911) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3926) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3953) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4065) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4096) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4142) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4252) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4436) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4477) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4503) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4520) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4597) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(5361) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6171) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6280) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6318) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6391) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(7280) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(8337) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(9296) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10032) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10747) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10781) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10817) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10864) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10898) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(11764) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(12807) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(12819) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(12830) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(12843) | User defined pragma syn_black_box detected @N: : | stack limit increased to max Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Process completed successfully. # Mon Jul 18 09:34:52 2022 ###########################################################] ###########################################################[ @N: : | stack limit increased to max @N: : ctu_can_fd_libero_top.vhd(90) | Top entity is set to ctu_can_fd_libero_top. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst_ce.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_constants_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_frame_format.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_register_map.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_config_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/drv_stat_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/unary_ops_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/mux2.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_byte.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_preload.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sig_sync.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/access_signaler.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/address_decoder.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_mux.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_registers_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/cmn_reg_map_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/parity_calculator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_sync.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_types_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/id_transfer_pkg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_destuffing.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_stuffing.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_traffic_counters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/crc_calc.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_counters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_rules.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/endian_swapper.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dlc_decoder.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/reintegration_counter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/retransmitt_counter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_shift_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_shift_reg.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_mux.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_err_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_edge_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trv_delay_meas.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sample_mux.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_module.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/clk_gate.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/priority_decoder.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_filter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/range_filter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_segment_meter.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_generator.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/synchronisation_checker.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/prescaler.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd'. @N:CD140 : | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ctu_can_fd_libero_top.vhd'. VHDL syntax check successful! @N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000". @N:CD630 : ctu_can_fd_libero_top.vhd(90) | Synthesizing ctu_can_fd_rtl.ctu_can_fd_libero_top.rtl. @N:CD630 : can_top_level.vhd(103) | Synthesizing ctu_can_fd_rtl.can_top_level.rtl. @N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time. @N:CD630 : bus_sampling.vhd(97) | Synthesizing ctu_can_fd_rtl.bus_sampling.rtl. @N:CD630 : sample_mux.vhd(93) | Synthesizing ctu_can_fd_rtl.sample_mux.rtl. Post processing for ctu_can_fd_rtl.sample_mux.rtl Running optimization stage 1 on sample_mux ....... Finished optimization stage 1 on sample_mux (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB) @N:CD630 : bit_err_detector.vhd(95) | Synthesizing ctu_can_fd_rtl.bit_err_detector.rtl. Post processing for ctu_can_fd_rtl.bit_err_detector.rtl Running optimization stage 1 on bit_err_detector ....... Finished optimization stage 1 on bit_err_detector (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB) @N:CD630 : tx_data_cache.vhd(94) | Synthesizing ctu_can_fd_rtl.tx_data_cache.rtl. Post processing for ctu_can_fd_rtl.tx_data_cache.rtl Running optimization stage 1 on tx_data_cache ....... Finished optimization stage 1 on tx_data_cache (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB) @N:CD630 : ssp_generator.vhd(94) | Synthesizing ctu_can_fd_rtl.ssp_generator.rtl. Post processing for ctu_can_fd_rtl.ssp_generator.rtl Running optimization stage 1 on ssp_generator ....... Finished optimization stage 1 on ssp_generator (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB) @N:CD630 : dff_arst.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst.rtl. Post processing for ctu_can_fd_rtl.dff_arst.rtl Running optimization stage 1 on dff_arst ....... Finished optimization stage 1 on dff_arst (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB) @N:CD630 : rst_reg.vhd(82) | Synthesizing ctu_can_fd_rtl.rst_reg.rtl. @N:CD630 : mux2.vhd(89) | Synthesizing ctu_can_fd_rtl.mux2.rtl. Post processing for ctu_can_fd_rtl.mux2.rtl Running optimization stage 1 on mux2 ....... Finished optimization stage 1 on mux2 (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB) Post processing for ctu_can_fd_rtl.rst_reg.rtl Running optimization stage 1 on rst_reg ....... Finished optimization stage 1 on rst_reg (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB) @N:CD630 : data_edge_detector.vhd(109) | Synthesizing ctu_can_fd_rtl.data_edge_detector.rtl. Post processing for ctu_can_fd_rtl.data_edge_detector.rtl Running optimization stage 1 on data_edge_detector ....... Finished optimization stage 1 on data_edge_detector (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB) @N:CD630 : trv_delay_meas.vhd(142) | Synthesizing ctu_can_fd_rtl.trv_delay_measurement.rtl. Post processing for ctu_can_fd_rtl.trv_delay_measurement.rtl Running optimization stage 1 on trv_delay_measurement ....... Finished optimization stage 1 on trv_delay_measurement (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB) @N:CD630 : sig_sync.vhd(77) | Synthesizing ctu_can_fd_rtl.sig_sync.rtl. Post processing for ctu_can_fd_rtl.sig_sync.rtl Running optimization stage 1 on sig_sync ....... Finished optimization stage 1 on sig_sync (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB) Post processing for ctu_can_fd_rtl.bus_sampling.rtl Running optimization stage 1 on bus_sampling ....... Finished optimization stage 1 on bus_sampling (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB) @N:CD630 : prescaler.vhd(100) | Synthesizing ctu_can_fd_rtl.prescaler.rtl. @N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time. @N:CD630 : trigger_generator.vhd(122) | Synthesizing ctu_can_fd_rtl.trigger_generator.rtl. Post processing for ctu_can_fd_rtl.trigger_generator.rtl Running optimization stage 1 on trigger_generator ....... Finished optimization stage 1 on trigger_generator (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB) @N:CD630 : bit_time_fsm.vhd(95) | Synthesizing ctu_can_fd_rtl.bit_time_fsm.rtl. @N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time. Post processing for ctu_can_fd_rtl.bit_time_fsm.rtl Running optimization stage 1 on bit_time_fsm ....... Finished optimization stage 1 on bit_time_fsm (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB) @N:CD630 : segment_end_detector.vhd(96) | Synthesizing ctu_can_fd_rtl.segment_end_detector.rtl. Post processing for ctu_can_fd_rtl.segment_end_detector.rtl Running optimization stage 1 on segment_end_detector ....... Finished optimization stage 1 on segment_end_detector (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB) @N:CD630 : bit_time_counters.vhd(98) | Synthesizing ctu_can_fd_rtl.bit_time_counters.rtl. Post processing for ctu_can_fd_rtl.bit_time_counters.rtl Running optimization stage 1 on bit_time_counters ....... Finished optimization stage 1 on bit_time_counters (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 150MB) @N:CD630 : bit_segment_meter.vhd(196) | Synthesizing ctu_can_fd_rtl.bit_segment_meter.rtl. Post processing for ctu_can_fd_rtl.bit_segment_meter.rtl Running optimization stage 1 on bit_segment_meter ....... Finished optimization stage 1 on bit_segment_meter (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB) @N:CD630 : synchronisation_checker.vhd(94) | Synthesizing ctu_can_fd_rtl.synchronisation_checker.rtl. Post processing for ctu_can_fd_rtl.synchronisation_checker.rtl Running optimization stage 1 on synchronisation_checker ....... Finished optimization stage 1 on synchronisation_checker (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB) @N:CD630 : bit_time_cfg_capture.vhd(96) | Synthesizing ctu_can_fd_rtl.bit_time_cfg_capture.rtl. Post processing for ctu_can_fd_rtl.bit_time_cfg_capture.rtl Running optimization stage 1 on bit_time_cfg_capture ....... Finished optimization stage 1 on bit_time_cfg_capture (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB) Post processing for ctu_can_fd_rtl.prescaler.rtl Running optimization stage 1 on prescaler ....... Finished optimization stage 1 on prescaler (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB) @N:CD630 : can_core.vhd(100) | Synthesizing ctu_can_fd_rtl.can_core.rtl. @N:CD630 : trigger_mux.vhd(108) | Synthesizing ctu_can_fd_rtl.trigger_mux.rtl. @N:CD630 : dff_arst_ce.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst_ce.rtl. Post processing for ctu_can_fd_rtl.dff_arst_ce.rtl Running optimization stage 1 on dff_arst_ce ....... Finished optimization stage 1 on dff_arst_ce (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB) Post processing for ctu_can_fd_rtl.trigger_mux.rtl Running optimization stage 1 on trigger_mux ....... Finished optimization stage 1 on trigger_mux (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB) @N:CD630 : bus_traffic_counters.vhd(92) | Synthesizing ctu_can_fd_rtl.bus_traffic_counters.rtl. Post processing for ctu_can_fd_rtl.bus_traffic_counters.rtl Running optimization stage 1 on bus_traffic_counters ....... Finished optimization stage 1 on bus_traffic_counters (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB) @N:CD630 : bit_destuffing.vhd(102) | Synthesizing ctu_can_fd_rtl.bit_destuffing.rtl. @N:CD630 : dff_arst_ce.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst_ce.rtl. Post processing for ctu_can_fd_rtl.dff_arst_ce.rtl Running optimization stage 1 on dff_arst_ce ....... Finished optimization stage 1 on dff_arst_ce (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB) @N:CD630 : dff_arst.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst.rtl. Post processing for ctu_can_fd_rtl.dff_arst.rtl Running optimization stage 1 on dff_arst ....... Finished optimization stage 1 on dff_arst (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB) Post processing for ctu_can_fd_rtl.bit_destuffing.rtl Running optimization stage 1 on bit_destuffing ....... Finished optimization stage 1 on bit_destuffing (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB) @N:CD630 : bit_stuffing.vhd(100) | Synthesizing ctu_can_fd_rtl.bit_stuffing.rtl. Post processing for ctu_can_fd_rtl.bit_stuffing.rtl Running optimization stage 1 on bit_stuffing ....... Finished optimization stage 1 on bit_stuffing (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB) @N:CD630 : can_crc.vhd(104) | Synthesizing ctu_can_fd_rtl.can_crc.rtl. @N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl. Post processing for ctu_can_fd_rtl.crc_calc.rtl Running optimization stage 1 on crc_calc ....... Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB) @N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl. Post processing for ctu_can_fd_rtl.crc_calc.rtl Running optimization stage 1 on crc_calc ....... Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB) @N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl. Post processing for ctu_can_fd_rtl.crc_calc.rtl Running optimization stage 1 on crc_calc ....... Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB) Post processing for ctu_can_fd_rtl.can_crc.rtl Running optimization stage 1 on can_crc ....... Finished optimization stage 1 on can_crc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB) @N:CD630 : fault_confinement.vhd(94) | Synthesizing ctu_can_fd_rtl.fault_confinement.rtl. @N:CD630 : fault_confinement_rules.vhd(94) | Synthesizing ctu_can_fd_rtl.fault_confinement_rules.rtl. Post processing for ctu_can_fd_rtl.fault_confinement_rules.rtl Running optimization stage 1 on fault_confinement_rules ....... Finished optimization stage 1 on fault_confinement_rules (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB) @N:CD630 : err_counters.vhd(100) | Synthesizing ctu_can_fd_rtl.err_counters.rtl. Post processing for ctu_can_fd_rtl.err_counters.rtl Running optimization stage 1 on err_counters ....... Finished optimization stage 1 on err_counters (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB) @N:CD630 : fault_confinement_fsm.vhd(96) | Synthesizing ctu_can_fd_rtl.fault_confinement_fsm.rtl. @N:CD233 : can_types_pkg.vhd(91) | Using sequential encoding for type t_fault_conf_state. Post processing for ctu_can_fd_rtl.fault_confinement_fsm.rtl Running optimization stage 1 on fault_confinement_fsm ....... Finished optimization stage 1 on fault_confinement_fsm (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB) Post processing for ctu_can_fd_rtl.fault_confinement.rtl Running optimization stage 1 on fault_confinement ....... Finished optimization stage 1 on fault_confinement (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB) @N:CD630 : operation_control.vhd(93) | Synthesizing ctu_can_fd_rtl.operation_control.rtl. @N:CD233 : can_types_pkg.vhd(98) | Using sequential encoding for type t_operation_control_state. Post processing for ctu_can_fd_rtl.operation_control.rtl Running optimization stage 1 on operation_control ....... Finished optimization stage 1 on operation_control (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB) @N:CD630 : protocol_control.vhd(98) | Synthesizing ctu_can_fd_rtl.protocol_control.rtl. @N:CD630 : rx_shift_reg.vhd(98) | Synthesizing ctu_can_fd_rtl.rx_shift_reg.rtl. @N:CD630 : shift_reg_byte.vhd(85) | Synthesizing ctu_can_fd_rtl.shift_reg_byte.rtl. Post processing for ctu_can_fd_rtl.shift_reg_byte.rtl Running optimization stage 1 on shift_reg_byte ....... Finished optimization stage 1 on shift_reg_byte (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB) Post processing for ctu_can_fd_rtl.rx_shift_reg.rtl Running optimization stage 1 on rx_shift_reg ....... Finished optimization stage 1 on rx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB) @N:CD630 : tx_shift_reg.vhd(95) | Synthesizing ctu_can_fd_rtl.tx_shift_reg.rtl. @N:CD630 : shift_reg_preload.vhd(77) | Synthesizing ctu_can_fd_rtl.shift_reg_preload.rtl. Post processing for ctu_can_fd_rtl.shift_reg_preload.rtl Running optimization stage 1 on shift_reg_preload ....... Finished optimization stage 1 on shift_reg_preload (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB) Post processing for ctu_can_fd_rtl.tx_shift_reg.rtl Running optimization stage 1 on tx_shift_reg ....... Finished optimization stage 1 on tx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB) @N:CD630 : err_detector.vhd(97) | Synthesizing ctu_can_fd_rtl.err_detector.rtl. Post processing for ctu_can_fd_rtl.err_detector.rtl Running optimization stage 1 on err_detector ....... Finished optimization stage 1 on err_detector (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB) @N:CD630 : retransmitt_counter.vhd(95) | Synthesizing ctu_can_fd_rtl.retransmitt_counter.rtl. Post processing for ctu_can_fd_rtl.retransmitt_counter.rtl Running optimization stage 1 on retransmitt_counter ....... Finished optimization stage 1 on retransmitt_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB) @N:CD630 : reintegration_counter.vhd(93) | Synthesizing ctu_can_fd_rtl.reintegration_counter.rtl. Post processing for ctu_can_fd_rtl.reintegration_counter.rtl Running optimization stage 1 on reintegration_counter ....... Finished optimization stage 1 on reintegration_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB) @N:CD630 : control_counter.vhd(97) | Synthesizing ctu_can_fd_rtl.control_counter.rtl. Post processing for ctu_can_fd_rtl.control_counter.rtl Running optimization stage 1 on control_counter ....... Finished optimization stage 1 on control_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB) @N:CD630 : protocol_control_fsm.vhd(110) | Synthesizing ctu_can_fd_rtl.protocol_control_fsm.rtl. @N:CD231 : can_types_pkg.vhd(106) | Using onehot encoding for type t_protocol_control_state. For example, enumeration s_pc_off is mapped to "10000000000000000000000000000000000000". @N:CD630 : dlc_decoder.vhd(88) | Synthesizing ctu_can_fd_rtl.dlc_decoder.rtl. Post processing for ctu_can_fd_rtl.dlc_decoder.rtl Running optimization stage 1 on dlc_decoder ....... Finished optimization stage 1 on dlc_decoder (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 158MB) Post processing for ctu_can_fd_rtl.protocol_control_fsm.rtl Running optimization stage 1 on protocol_control_fsm ....... Finished optimization stage 1 on protocol_control_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) @N:CD630 : endian_swapper.vhd(95) | Synthesizing ctu_can_fd_rtl.endian_swapper.rtl. Post processing for ctu_can_fd_rtl.endian_swapper.rtl Running optimization stage 1 on endian_swapper ....... Finished optimization stage 1 on endian_swapper (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) Post processing for ctu_can_fd_rtl.protocol_control.rtl Running optimization stage 1 on protocol_control ....... Finished optimization stage 1 on protocol_control (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) Post processing for ctu_can_fd_rtl.can_core.rtl Running optimization stage 1 on can_core ....... Finished optimization stage 1 on can_core (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) @N:CD630 : int_manager.vhd(97) | Synthesizing ctu_can_fd_rtl.int_manager.rtl. @N:CD630 : int_module.vhd(103) | Synthesizing ctu_can_fd_rtl.int_module.rtl. Post processing for ctu_can_fd_rtl.int_module.rtl Running optimization stage 1 on int_module ....... Finished optimization stage 1 on int_module (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) Post processing for ctu_can_fd_rtl.int_manager.rtl Running optimization stage 1 on int_manager ....... Finished optimization stage 1 on int_manager (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) @N:CD630 : frame_filters.vhd(101) | Synthesizing ctu_can_fd_rtl.frame_filters.rtl. @N:CD630 : range_filter.vhd(94) | Synthesizing ctu_can_fd_rtl.range_filter.rtl. Post processing for ctu_can_fd_rtl.range_filter.rtl Running optimization stage 1 on range_filter ....... Finished optimization stage 1 on range_filter (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) @N:CD630 : bit_filter.vhd(92) | Synthesizing ctu_can_fd_rtl.bit_filter.rtl. Post processing for ctu_can_fd_rtl.bit_filter.rtl Running optimization stage 1 on bit_filter ....... Finished optimization stage 1 on bit_filter (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) Post processing for ctu_can_fd_rtl.frame_filters.rtl Running optimization stage 1 on frame_filters ....... Finished optimization stage 1 on frame_filters (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) @N:CD630 : tx_arbitrator.vhd(100) | Synthesizing ctu_can_fd_rtl.tx_arbitrator.rtl. @N:CD630 : tx_arbitrator_fsm.vhd(98) | Synthesizing ctu_can_fd_rtl.tx_arbitrator_fsm.rtl. @N:CD231 : can_types_pkg.vhd(173) | Using onehot encoding for type t_tx_arb_state. For example, enumeration s_arb_idle is mapped to "10000000". Post processing for ctu_can_fd_rtl.tx_arbitrator_fsm.rtl Running optimization stage 1 on tx_arbitrator_fsm ....... Finished optimization stage 1 on tx_arbitrator_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) @N:CD630 : priority_decoder.vhd(96) | Synthesizing ctu_can_fd_rtl.priority_decoder.rtl. @N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized. @N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized. @N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized. @N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized. @N:CD604 : priority_decoder.vhd(278) | OTHERS clause is not synthesized. @N:CD604 : priority_decoder.vhd(278) | OTHERS clause is not synthesized. Post processing for ctu_can_fd_rtl.priority_decoder.rtl Running optimization stage 1 on priority_decoder ....... Finished optimization stage 1 on priority_decoder (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB) Post processing for ctu_can_fd_rtl.tx_arbitrator.rtl Running optimization stage 1 on tx_arbitrator ....... Finished optimization stage 1 on tx_arbitrator (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. @N:CD630 : parity_calculator.vhd(78) | Synthesizing ctu_can_fd_rtl.parity_calculator.rtl. Post processing for ctu_can_fd_rtl.parity_calculator.rtl Running optimization stage 1 on parity_calculator ....... Finished optimization stage 1 on parity_calculator (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : inf_ram_wrapper.vhd(85) | Synthesizing ctu_can_fd_rtl.inf_ram_wrapper.rtl. Post processing for ctu_can_fd_rtl.inf_ram_wrapper.rtl Running optimization stage 1 on inf_ram_wrapper ....... Finished optimization stage 1 on inf_ram_wrapper (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : clk_gate.vhd(83) | Synthesizing ctu_can_fd_rtl.clk_gate.rtl. Post processing for ctu_can_fd_rtl.clk_gate.rtl Running optimization stage 1 on clk_gate ....... Finished optimization stage 1 on clk_gate (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl. @N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000". Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl Running optimization stage 1 on txt_buffer_fsm ....... Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl. Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl Running optimization stage 1 on txt_buffer_ram ....... Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) Post processing for ctu_can_fd_rtl.txt_buffer.rtl Running optimization stage 1 on txt_buffer ....... Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB) @N:CD630 : rx_buffer.vhd(99) | Synthesizing ctu_can_fd_rtl.rx_buffer.rtl. @N:CD364 : rx_buffer.vhd(793) | Removing redundant assignment. @N:CD364 : rx_buffer.vhd(824) | Removing redundant assignment. @N:CD630 : rx_buffer_ram.vhd(105) | Synthesizing ctu_can_fd_rtl.rx_buffer_ram.rtl. @N:CD630 : inf_ram_wrapper.vhd(85) | Synthesizing ctu_can_fd_rtl.inf_ram_wrapper.rtl. Post processing for ctu_can_fd_rtl.inf_ram_wrapper.rtl Running optimization stage 1 on inf_ram_wrapper ....... Finished optimization stage 1 on inf_ram_wrapper (CPU Time 0h:00m:00s, Memory Used current: 182MB peak: 185MB) Post processing for ctu_can_fd_rtl.rx_buffer_ram.rtl Running optimization stage 1 on rx_buffer_ram ....... Finished optimization stage 1 on rx_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB) @N:CD630 : rx_buffer_pointers.vhd(101) | Synthesizing ctu_can_fd_rtl.rx_buffer_pointers.rtl. Post processing for ctu_can_fd_rtl.rx_buffer_pointers.rtl Running optimization stage 1 on rx_buffer_pointers ....... Finished optimization stage 1 on rx_buffer_pointers (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB) @N:CD630 : rx_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.rx_buffer_fsm.rtl. @N:CD231 : can_types_pkg.vhd(161) | Using onehot encoding for type t_rx_buf_state. For example, enumeration s_rxb_idle is mapped to "10000000". Post processing for ctu_can_fd_rtl.rx_buffer_fsm.rtl Running optimization stage 1 on rx_buffer_fsm ....... Finished optimization stage 1 on rx_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB) Post processing for ctu_can_fd_rtl.rx_buffer.rtl Running optimization stage 1 on rx_buffer ....... Finished optimization stage 1 on rx_buffer (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB) @N:CD630 : memory_registers.vhd(97) | Synthesizing ctu_can_fd_rtl.memory_registers.rtl. @N:CD630 : test_registers_reg_map.vhd(81) | Synthesizing ctu_can_fd_rtl.test_registers_reg_map.rtl. @N:CD630 : data_mux.vhd(74) | Synthesizing ctu_can_fd_rtl.data_mux.rtl. Post processing for ctu_can_fd_rtl.data_mux.rtl Running optimization stage 1 on data_mux ....... Finished optimization stage 1 on data_mux (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 193MB) @N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl. Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 193MB) @N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl. Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB) @N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl. Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB) @N:CD630 : address_decoder.vhd(41) | Synthesizing ctu_can_fd_rtl.address_decoder.rtl. Post processing for ctu_can_fd_rtl.address_decoder.rtl Running optimization stage 1 on address_decoder ....... Finished optimization stage 1 on address_decoder (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB) Post processing for ctu_can_fd_rtl.test_registers_reg_map.rtl Running optimization stage 1 on test_registers_reg_map ....... Finished optimization stage 1 on test_registers_reg_map (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB) @N:CD630 : control_registers_reg_map.vhd(81) | Synthesizing ctu_can_fd_rtl.control_registers_reg_map.rtl. @N:CD630 : data_mux.vhd(74) | Synthesizing ctu_can_fd_rtl.data_mux.rtl. Post processing for ctu_can_fd_rtl.data_mux.rtl Running optimization stage 1 on data_mux ....... Finished optimization stage 1 on data_mux (CPU Time 0h:00m:03s, Memory Used current: 373MB peak: 373MB) @N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl. Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB) Only the first 100 messages of id 'CD630' are reported. To see all messages use 'report_messages -log /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/synlog/ctu_can_fd_libero_top_compiler.srr -id CD630' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CD630} -count unlimited' in the Tcl shell. Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB) Post processing for ctu_can_fd_rtl.access_signaller.rtl Running optimization stage 1 on access_signaller ....... Finished optimization stage 1 on access_signaller (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Post processing for ctu_can_fd_rtl.memory_reg.rtl Running optimization stage 1 on memory_reg ....... Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Post processing for ctu_can_fd_rtl.address_decoder.rtl Running optimization stage 1 on address_decoder ....... Finished optimization stage 1 on address_decoder (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Post processing for ctu_can_fd_rtl.control_registers_reg_map.rtl Running optimization stage 1 on control_registers_reg_map ....... Finished optimization stage 1 on control_registers_reg_map (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Post processing for ctu_can_fd_rtl.memory_registers.rtl Running optimization stage 1 on memory_registers ....... Finished optimization stage 1 on memory_registers (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Post processing for ctu_can_fd_rtl.rst_sync.rtl Running optimization stage 1 on rst_sync ....... Finished optimization stage 1 on rst_sync (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Post processing for ctu_can_fd_rtl.can_top_level.rtl Running optimization stage 1 on can_top_level ....... Finished optimization stage 1 on can_top_level (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Post processing for ctu_can_fd_rtl.ctu_can_fd_libero_top.rtl Running optimization stage 1 on ctu_can_fd_libero_top ....... Finished optimization stage 1 on ctu_can_fd_libero_top (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ....... @N:CL159 : address_decoder.vhd(64) | Input clk_sys is unused. @N:CL159 : address_decoder.vhd(65) | Input res_n is unused. Finished optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 11 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL247 : memory_reg.vhd(76) | Input port bit 0 of data_in(31 downto 0) is unused @W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : memory_reg.vhd(70) | Input clk_sys is unused. @N:CL159 : memory_reg.vhd(71) | Input res_n is unused. @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : memory_reg.vhd(70) | Input clk_sys is unused. @N:CL159 : memory_reg.vhd(71) | Input res_n is unused. @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0 ....... Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0 ....... @W:CL247 : memory_reg.vhd(76) | Input port bit 18 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 12 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 6 of data_in(31 downto 0) is unused Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0 ....... Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0 ....... Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 13 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 29 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0 ....... @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 7 to 1 of data_in(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @N:CL159 : access_signaler.vhd(65) | Input clk_sys is unused. @N:CL159 : access_signaler.vhd(66) | Input res_n is unused. @N:CL159 : access_signaler.vhd(77) | Input write is unused. Finished optimization stage 2 on access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 7 to 3 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0 ....... @W:CL247 : memory_reg.vhd(76) | Input port bit 31 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 27 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 23 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 19 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 15 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 11 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 7 of data_in(31 downto 0) is unused @W:CL247 : memory_reg.vhd(76) | Input port bit 3 of data_in(31 downto 0) is unused @N:CL159 : memory_reg.vhd(84) | Input lock is unused. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 10 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ....... Finished optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @W:CL246 : control_registers_reg_map.vhd(97) | Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : control_registers_reg_map.vhd(97) | Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @N:CL159 : address_decoder.vhd(64) | Input clk_sys is unused. @N:CL159 : address_decoder.vhd(65) | Input res_n is unused. Finished optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 2 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 1 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ....... @W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 20 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL247 : memory_reg.vhd(79) | Input port bit 3 of w_be(3 downto 0) is unused Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 ....... Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @W:CL246 : test_registers_reg_map.vhd(92) | Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : test_registers_reg_map.vhd(92) | Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : test_registers_reg_map.vhd(100) | Input lock_2 is unused. Finished optimization stage 2 on test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB) Running optimization stage 2 on memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @W:CL246 : memory_registers.vhd(196) | Input port bits 511 to 386 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL247 : memory_registers.vhd(196) | Input port bit 383 of stat_bus(511 downto 0) is unused @W:CL246 : memory_registers.vhd(196) | Input port bits 369 to 306 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : memory_registers.vhd(196) | Input port bits 299 to 297 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : memory_registers.vhd(196) | Input port bits 256 to 252 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : memory_registers.vhd(196) | Input port bits 187 to 110 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : memory_registers.vhd(196) | Input port bits 98 to 90 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL247 : memory_registers.vhd(196) | Input port bit 80 of stat_bus(511 downto 0) is unused @W:CL246 : memory_registers.vhd(196) | Input port bits 70 to 10 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : memory_registers.vhd(196) | Input port bits 8 to 6 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on rx_buffer_fsm ....... @N:CL201 : rx_buffer_fsm.vhd(311) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on rx_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on rx_buffer_pointers_128 ....... Finished optimization stage 2 on rx_buffer_pointers_128 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on inf_ram_wrapper_32_128_12_true_true ....... @W:CL246 : inf_ram_wrapper.vhd(114) | Input port bits 11 to 7 of addr_a(11 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : inf_ram_wrapper.vhd(129) | Input port bits 11 to 7 of addr_b(11 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on inf_ram_wrapper_32_128_12_true_true (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on rx_buffer_ram_128_true_true ....... @N:CL134 : rx_buffer_ram.vhd(237) | Found RAM parity, depth=128, width=1 @W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 47 to 44 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on rx_buffer_ram_128_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on rx_buffer_128_true_true_1 ....... @W:CL246 : rx_buffer.vhd(224) | Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : rx_buffer.vhd(224) | Input port bits 475 to 355 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : rx_buffer.vhd(224) | Input port bits 349 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on rx_buffer_128_true_true_1 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_ram_0_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_0_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_fsm_0 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_8_0_1_true_true ....... @W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 1 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused. Finished optimization stage 2 on txt_buffer_8_0_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_ram_1_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_fsm_1 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_1 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_8_1_1_true_true ....... @W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 2 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL247 : txt_buffer.vhd(150) | Input port bit 0 of txtb_sw_cmd_index(7 downto 0) is unused Finished optimization stage 2 on txt_buffer_8_1_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_ram_2_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_2_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_fsm_2 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_2 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_8_2_1_true_true ....... @W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 3 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer.vhd(150) | Input port bits 1 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused. Finished optimization stage 2 on txt_buffer_8_2_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_ram_3_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_3_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_fsm_3 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_3 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_8_3_1_true_true ....... @W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 4 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer.vhd(150) | Input port bits 2 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_8_3_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_ram_4_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_4_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_fsm_4 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_4 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_8_4_1_true_true ....... @W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 5 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer.vhd(150) | Input port bits 3 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused. Finished optimization stage 2 on txt_buffer_8_4_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_ram_5_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_5_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_fsm_5 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_5 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_8_5_1_true_true ....... @W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 6 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer.vhd(150) | Input port bits 4 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_8_5_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_ram_6_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_6_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_fsm_6 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_6 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on txt_buffer_8_6_1_true_true ....... @W:CL247 : txt_buffer.vhd(150) | Input port bit 7 of txtb_sw_cmd_index(7 downto 0) is unused @W:CL246 : txt_buffer.vhd(150) | Input port bits 5 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused. Finished optimization stage 2 on txt_buffer_8_6_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on clk_gate_1 ....... @N:CL159 : clk_gate.vhd(92) | Input clk_en is unused. @N:CL159 : clk_gate.vhd(95) | Input scan_enable is unused. Finished optimization stage 2 on clk_gate_1 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB) Running optimization stage 2 on inf_ram_wrapper_32_21_5_true_true ....... Finished optimization stage 2 on inf_ram_wrapper_32_21_5_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on txt_buffer_ram_7_true_true ....... @N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1 @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_ram_7_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on txt_buffer_fsm_7 ....... @N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Finished optimization stage 2 on txt_buffer_fsm_7 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on txt_buffer_8_7_1_true_true ....... @W:CL246 : txt_buffer.vhd(150) | Input port bits 6 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on txt_buffer_8_7_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on priority_decoder_8 ....... Finished optimization stage 2 on priority_decoder_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on tx_arbitrator_fsm ....... @N:CL201 : tx_arbitrator_fsm.vhd(524) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 @W:CL246 : tx_arbitrator_fsm.vhd(128) | Input port bits 5 to 2 of txtb_hw_cmd(5 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on tx_arbitrator_fsm (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on tx_arbitrator_8 ....... @W:CL247 : tx_arbitrator.vhd(125) | Input port bit 7 of txtb_allow_bb(7 downto 0) is unused @W:CL247 : tx_arbitrator.vhd(125) | Input port bit 5 of txtb_allow_bb(7 downto 0) is unused @W:CL247 : tx_arbitrator.vhd(125) | Input port bit 3 of txtb_allow_bb(7 downto 0) is unused @W:CL247 : tx_arbitrator.vhd(125) | Input port bit 1 of txtb_allow_bb(7 downto 0) is unused @W:CL246 : tx_arbitrator.vhd(200) | Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : tx_arbitrator.vhd(200) | Input port bits 474 to 473 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : tx_arbitrator.vhd(200) | Input port bits 471 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on tx_arbitrator_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_filter_29_true ....... Finished optimization stage 2 on bit_filter_29_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on range_filter_29_true ....... Finished optimization stage 2 on range_filter_29_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on frame_filters_true_true_true_true ....... @W:CL246 : frame_filters.vhd(129) | Input port bits 1023 to 331 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : frame_filters.vhd(129) | Input port bits 80 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on frame_filters_true_true_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on int_module ....... Finished optimization stage 2 on int_module (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on int_manager_12_8 ....... @W:CL246 : int_manager.vhd(157) | Input port bits 1023 to 876 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : int_manager.vhd(157) | Input port bits 863 to 844 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : int_manager.vhd(157) | Input port bits 831 to 812 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : int_manager.vhd(157) | Input port bits 799 to 780 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : int_manager.vhd(157) | Input port bits 767 to 748 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : int_manager.vhd(157) | Input port bits 735 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on int_manager_12_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on endian_swapper_true_4_8 ....... Finished optimization stage 2 on endian_swapper_true_4_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on dlc_decoder ....... Finished optimization stage 2 on dlc_decoder (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on protocol_control_fsm ....... @N:CL201 : protocol_control_fsm.vhd(2988) | Trying to extract state machine for register sp_control_q_i. Extracted state machine for register sp_control_q_i State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : protocol_control_fsm.vhd(2840) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 38 reachable states with original encodings of: 00000000000000000000000000000000000001 00000000000000000000000000000000000010 00000000000000000000000000000000000100 00000000000000000000000000000000001000 00000000000000000000000000000000010000 00000000000000000000000000000000100000 00000000000000000000000000000001000000 00000000000000000000000000000010000000 00000000000000000000000000000100000000 00000000000000000000000000001000000000 00000000000000000000000000010000000000 00000000000000000000000000100000000000 00000000000000000000000001000000000000 00000000000000000000000010000000000000 00000000000000000000000100000000000000 00000000000000000000001000000000000000 00000000000000000000010000000000000000 00000000000000000000100000000000000000 00000000000000000001000000000000000000 00000000000000000010000000000000000000 00000000000000000100000000000000000000 00000000000000001000000000000000000000 00000000000000010000000000000000000000 00000000000000100000000000000000000000 00000000000001000000000000000000000000 00000000000010000000000000000000000000 00000000000100000000000000000000000000 00000000001000000000000000000000000000 00000000010000000000000000000000000000 00000000100000000000000000000000000000 00000001000000000000000000000000000000 00000010000000000000000000000000000000 00000100000000000000000000000000000000 00001000000000000000000000000000000000 00010000000000000000000000000000000000 00100000000000000000000000000000000000 01000000000000000000000000000000000000 10000000000000000000000000000000000000 Finished optimization stage 2 on protocol_control_fsm (CPU Time 0h:00m:02s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on control_counter_9 ....... Finished optimization stage 2 on control_counter_9 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on reintegration_counter ....... Finished optimization stage 2 on reintegration_counter (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on retransmitt_counter_4 ....... Finished optimization stage 2 on retransmitt_counter_4 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on err_detector_true ....... Finished optimization stage 2 on err_detector_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on tx_shift_reg ....... Finished optimization stage 2 on tx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @W:CL247 : shift_reg_byte.vhd(117) | Input port bit 0 of byte_input_sel(3 downto 0) is unused Finished optimization stage 2 on shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on rx_shift_reg ....... Finished optimization stage 2 on rx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on protocol_control_9_4_true ....... @W:CL246 : protocol_control.vhd(128) | Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : protocol_control.vhd(128) | Input port bits 506 to 478 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : protocol_control.vhd(128) | Input port bits 476 to 472 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : protocol_control.vhd(128) | Input port bits 464 to 461 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : protocol_control.vhd(128) | Input port bits 459 to 430 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : protocol_control.vhd(128) | Input port bits 428 to 375 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : protocol_control.vhd(128) | Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on protocol_control_9_4_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on operation_control ....... @N:CL201 : operation_control.vhd(227) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on operation_control (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on fault_confinement_fsm ....... @N:CL201 : fault_confinement_fsm.vhd(274) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 3 reachable states with original encodings of: 00 01 10 Finished optimization stage 2 on fault_confinement_fsm (CPU Time 0h:00m:01s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on err_counters ....... Finished optimization stage 2 on err_counters (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on fault_confinement_rules ....... @N:CL159 : fault_confinement_rules.vhd(100) | Input clk_sys is unused. Finished optimization stage 2 on fault_confinement_rules (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on fault_confinement ....... @W:CL246 : fault_confinement.vhd(114) | Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : fault_confinement.vhd(114) | Input port bits 512 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : fault_confinement.vhd(114) | Input port bits 508 to 427 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : fault_confinement.vhd(114) | Input port bits 399 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @N:CL159 : fault_confinement.vhd(163) | Input rec_valid is unused. Finished optimization stage 2 on fault_confinement (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ....... Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 ....... Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @W:CL246 : can_crc.vhd(129) | Input port bits 1023 to 511 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : can_crc.vhd(129) | Input port bits 509 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_stuffing ....... Finished optimization stage 2 on bit_stuffing (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ....... Finished optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 ....... Finished optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_destuffing ....... Finished optimization stage 2 on bit_destuffing (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bus_traffic_counters ....... Finished optimization stage 2 on bus_traffic_counters (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on trigger_mux_2 ....... Finished optimization stage 2 on trigger_mux_2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_time_cfg_capture_8_8_8_5_8_8_8_5 ....... @W:CL246 : bit_time_cfg_capture.vhd(136) | Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : bit_time_cfg_capture.vhd(136) | Input port bits 508 to 61 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on bit_time_cfg_capture_8_8_8_5_8_8_8_5 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on synchronisation_checker ....... Finished optimization stage 2 on synchronisation_checker (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_segment_meter_5_8_8_9 ....... Finished optimization stage 2 on bit_segment_meter_5_8_8_9 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_time_counters_9_8 ....... Finished optimization stage 2 on bit_time_counters_9_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on segment_end_detector ....... Finished optimization stage 2 on segment_end_detector (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_time_fsm ....... @N:CL201 : bit_time_fsm.vhd(208) | Trying to extract state machine for register current_state. Extracted state machine for register current_state State machine has 3 reachable states with original encodings of: 00 01 10 Finished optimization stage 2 on bit_time_fsm (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on trigger_generator_2 ....... Finished optimization stage 2 on trigger_generator_2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on prescaler_8_8_8_5_8_8_8_5_2 ....... Finished optimization stage 2 on prescaler_8_8_8_5_8_8_8_5_2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on trv_delay_measurement_7_8_true_255 ....... Finished optimization stage 2 on trv_delay_measurement_7_8_true_255 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on data_edge_detector ....... Finished optimization stage 2 on data_edge_detector (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on mux2 ....... Finished optimization stage 2 on mux2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... Finished optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on ssp_generator_15 ....... Finished optimization stage 2 on ssp_generator_15 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 ....... @N:CL134 : tx_data_cache.vhd(189) | Found RAM tx_cache, depth=8, width=1 Finished optimization stage 2 on tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bit_err_detector ....... Finished optimization stage 2 on bit_err_detector (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on sample_mux ....... Finished optimization stage 2 on sample_mux (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on bus_sampling_255_8_7_8_true_15 ....... @W:CL246 : bus_sampling.vhd(145) | Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : bus_sampling.vhd(145) | Input port bits 508 to 383 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. @W:CL246 : bus_sampling.vhd(145) | Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on bus_sampling_255_8_7_8_true_15 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ....... Finished optimization stage 2 on can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) Running optimization stage 2 on ctu_can_fd_libero_top ....... Finished optimization stage 2 on ctu_can_fd_libero_top (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_vhdl Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 382MB peak: 382MB) Process completed successfully. # Mon Jul 18 09:35:08 2022 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: S-2021.09M Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro OS: Ubuntu 20.04.4 LTS Hostname: ondrej-Aspire-V3-771 max virtual memory: unlimited (bytes) max user processes: 63079 max stack size: 8388608 (bytes) Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Jul 18 09:35:08 2022 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: ctu_can_fd_libero_top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 43MB peak: 43MB) Process took 0h:00m:16s realtime, 0h:00m:15s cputime Process completed successfully. # Mon Jul 18 09:35:08 2022 ###########################################################]