RE: [ethmac] rx_clk in loopback

[Illan Glasner <IGlasner@mrv.com>]

   Igor Hi,

      Usualy loopback is done by simple putting a fifo that yo write to it
with the recive clock and read from it with the trasmite clock.

it is also custom that since loopback is for debug and not for high
performance that if a packet have arrive while the fifo is not empty you can
discard it and the fifo can be as small as one packet only.

as for reading you simple need to compensate for the clock ppm so you can
verify the not-empty in the recive domain and syncornize it to the trasmite
domain this will be enough clocks or check the not-empty in the trasmite
domain and simple add FF's to delay the start of reading (2 FF's delay
should be sufficient)

and yes the solution is good for both fpga and Asic.

have a nice day

   Illan


-----Original Message-----
From: Igor Mohor [mailto:igorm@opencores.org]
Sent: Thursday, November 14, 2002 9:26 AM
To: Ethmac@Opencores. Org
Subject: [ethmac] rx_clk in loopback 


Hi, Guys.

I got a bug report that in loopback many packets are received with a CRC
error.
This happens because data and control signals are loopbacked while rx_clk
isn't.

So loopback signals are not synchronous with the rx_clk any more.

One solution would be to do something like
   rx_clk = loop_back ? tx_clk_pin : rx_clk_pin:

In this case we have a gated clock which I believe is a bad solution.

Another solution would be to somehow synchronize data and control signals to
tx_clk.
when in loopback.


Any good idea?

Solution must be good for both, FPGA and ASIC.

Regards,
	Igor



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