[ethmac] Ethernet progress

["Igor Mohor" <igorm@opencores.org>]

Hi, Guys.

For easier simulation I expanded Ethernet environment with:
- memory model (connected to the wishbone slave interface)
- host model (connected to the wishbone master interface)
- Traffic cop with 2 master and 2 slave interfaces (ethernet is connected to
  one master and one slave interface, host to second master and memory to
second slave)

Traffic cop is fully synthesizable and can be used in real design.

The testbench that is being written already uses this cop and models.


Regards,
	Igor

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