RE: [ethmac] Divided clock

["Tal Weiss" <tal@congruency.com>]

In RMII, since the clock is always 50MHz, when working in 10base-T data changes only once every 10 clocks.

You add clock_enable circuitry connected to a counter that counts to 10.

You know about the outcome of the autonegotiations through the SMI port, first register.

 

Tal.

 

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of zou.yixin@zte.com.cn
Sent: Thursday, November 22, 2001 1:14 PM
To: ethmac@opencores.org
Subject: RE: [ethmac] Divided clock

yes,it is a RMII port.

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主题:        RE: [ethmac] Divided clock

The clock in the MII configuration is an external 25MHz connected only to the PHY.
The phy handles the division and the RXCLOCK and TXCLOCK coming from the phy to the mac are always correct.
The is the case with all the MII phys I know (Broadcom, Kendin, Marvel, LSI, Davicom...).
 
In RMII it's a little different, and there is always only one external 50MHz clock.
 
Tal.
-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of zou.yixin@zte.com.cn
Sent: Thursday, November 22, 2001 11:18 AM
To: ethmac@opencores.org
Subject: RE: [ethmac] Divided clock


Thanks,Weiss.
I mean that if  the clock connected to PHY and MAC is an external clock (not provided by
the PHY),with a fixed frequency of 25M.I hope the MAC and PHY can change the TX and RX speed( not the
external clock frequency) smoothly after auto-negotiation.
Suppose the PHY can work in such case ,then what should I do in my MAC?
Can I divided the 25M clock to 2.5M?
or maintain the 25M clock ,just sample the data at 10th clock? But it seems difficult to modify my
internal logic.



yxzhou

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主题:        RE: [ethmac] Divided clock

Hello yxzhou,
 
The phy auto-negotiates with the other phy on the other side of the line. They come up with a mutual speed (10 or 100 mbps).
If the clock is 10 mbps the phy outputs 2.5mbps to the mac layer, so that the mac could send and receeive data on the 4 bit wide MII bus.
10MHz/4=2.5MHz
When the phys come up with 100mbps they output a 25 MHz clock (100MHz/4 = 25MHz).
 
I hope this helps.
 
Tal.
-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of zou.yixin@zte.com.cn
Sent: Thursday, November 22, 2001 7:43 AM
To: ethmac@opencores.org
Subject: [ethmac] Divided clock


Hi,
 The ethernet mac  support 10/100Mbps data rate.
It is said in the spec that MTxClk and MRxClk are provided by PHY ,which operate at 25MHz(100Bps) and 2.5M(10Mbps).

My question is:
If the clock to the MAC and PHY are provided by an external clock and the frequecy is 25MHz,
suppose they can determine the speed by auto-negotiation,then  how can they work at the rate of 10Mbps?
Is divided clock  necessary? Can you give me some advise on divided clock?

Thanks,
yxzhou