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RE: [ethmac] Divided clock

Hello yxzhou,
 
The phy auto-negotiates with the other phy on the other side of the line. They come up with a mutual speed (10 or 100 mbps).
If the clock is 10 mbps the phy outputs 2.5mbps to the mac layer, so that the mac could send and receeive data on the 4 bit wide MII bus.
10MHz/4=2.5MHz
When the phys come up with 100mbps they output a 25 MHz clock (100MHz/4 = 25MHz).
 
I hope this helps.
 
Tal.
-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of zou.yixin@zte.com.cn
Sent: Thursday, November 22, 2001 7:43 AM
To: ethmac@opencores.org
Subject: [ethmac] Divided clock


Hi,
   The ethernet mac  support 10/100Mbps data rate.
It is said in the spec that MTxClk and MRxClk are provided by PHY ,which operate at 25MHz(100Bps) and 2.5M(10Mbps).

My question is:
If the clock to the MAC and PHY are provided by an external clock and the frequecy is 25MHz,
suppose they can determine the speed by auto-negotiation,then  how can they work at the rate of 10Mbps?
Is divided clock  necessary? Can you give me some advise on divided clock?

Thanks,
yxzhou