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[cvs-checkins] pci/rtl/verilog pci_target32_sm.v



CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/09/24 17:30:36

Modified files:
	rtl/verilog    : pci_target32_sm.v 

Log message:
	Changed state machine encoding to true one-hot

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