[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] oc8051/syn/src/verilog oc8051_fpga_top.v



CVSROOT:	/home/oc/cvs
Module name:	oc8051
Changes by:	simont	02/09/03 14:22:08

Modified files:
	syn/src/verilog: oc8051_fpga_top.v 

Log message:
	added signals ack, stb and cyc
--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml