RE: [oc] vhdl question

[spyros_s@freemail.gr (spyros)]

hi all,

>- ---cut here---
>
>signal mid : std_logic;
>
>mid <= start OR clk;
>start <= '1' when mid='1' and addr(7 downto 0)="11111111" else '0';
>
>- ---cut here---

the above is wrong...sorry it was late in the night when i wrote it..(so it is now!!!)the correct (or i hope so this time..) code is:

signal mid : std_logic;
start <= '1' when (mid or read)='1' and addr(7 downto 0)="11111111" else '0';

keep the mid signal as many cycles as you wish to 1.

regards,
spyros

--
student @ Demokritos Univercity of THrace


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