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Re: [oc] Query abt Switch level modelling in Verilog



Hi John,
 
Thank you for the information.
But please let me know if the gate level primitives are being used by any one to try and emulate the hardware test environment to max possible extent, for example, using rcmos in place of pullup to model a very week pull-up on a net or in generating an SDRAM model at switch level or something else.
Also, I believe these basic switches are not synthesizable and are just meant for simulating hardware-- please correct me if I am wrong.
 
Thanks and regards,
R Ramakrishna

John Sheahan <jrsheahan@optushome.com.au> wrote:
On Sat, 2003-06-14 at 15:52, R. Ramakrishna wrote:
> Hi All,
>
> Can any one kindly answer my query? I want to know if the MOS switches and other lowest-level primitives that verilog supports are used by any one, either in their simulation environment or in their RTL code. If YES, then where exactly are they being used?
>
> Thanks in Advance!

they are useful/required creating gate level library models themselves,
used in a gate level sim.
john


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R Ramakrishna

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