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Re: [oc] netlist simulation
----- Original Message -----
From: jae lim <jlim0011@y... >
To: cores@o...
Date: Thu, 18 Jul 2002 14:20:03 -0700 (PDT)
Subject: [oc] netlist simulation
>
>
> Hello there
>
> here is the post synthesis file included in a test
> bench.
> It is just a small example. But when I use ncverilog
> simulate
> it, it gave me error saying that :
>
> Unbounded ncvlog: *W,UNBINS: Unbound instance found:
> U1::NR2 in unit worklib.prioritize:v
> ...........
>
> Is there anybody tell me why??
>
> Thanks a lot
>
> Have a nice weekend
>
> Xia
>
Hi
Looks like , the cell NR2/U1 (module priortize )is being compiled
before the vendor specific library file (which should contain the NR2
verilog primitive) is compiled .
Does this helps ?
-Manit
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