Re: ??: [oc] AMBA - SDR/DDR SDRAM controller

["kinysh asdf" <kinysh@hotmail.com>]

You can make it configurable.
the ddr clock can be 1/1, 1/2, 1/4 to ahb_clock.
because in realsystem the ddr clock will changes according to different 
board. however ahb clock changes little.

Bests
kinysh


>From: Rudolf Usselmann <rudi@asics.ws>
>Reply-To: cores@opencores.org
>To: cores@opencores.org
>Subject: Re: ??: [oc] AMBA - SDR/DDR SDRAM controller
>Date: Thu, 21 Nov 2002 10:25:32 +0700
>
>On Thursday 21 November 2002 09:17, Zhichong Chen (Beijing) wrote:
> > hi, rudi
> >
> > I have a question. Since AHB uses only rising edge and DDR using both
> > clock edge, is that means the frequency of HCLK is at least 2x frequency
> > of DDR clock?
>
>You have two option, make your HCLK 2x the DDR clock, or make your
>AHB bus twice the size of the DDR bus (e.g. AHB 64 bit, 32 bit DDR bus).
>
>rudi
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