RE: [oc] C to HDL? Didn't realise the situation was that bad

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Jim,

forgot to include this on the previous one

> I have a little squeak to make about this. A picky little point for sure.
> The point is that these tools do not technically permit you to program the
> FPGAs in C. Instead, by following specific guidelines and using well crafted
> #define macros you can use a C (C++) language subset to produce a common
> source for use in both simulation and programming of the FPGA. In other
> words. These are new languages that can be constructed using the C/C++
> compilers.

My translator is a "translator", I don't compile Verilog, I don't generate netlists
(as yet anyway). You put in "jim.c" and you get out "jim.v", the Verilog judging by
current results be easy to relate back to the original C and not "fudgy" as with
the #define MACRO to fudge C to HDL brigade use. Mention no names

http://www.adelantetechnologies.com/en/html/algemeen/Download/DesignExamples/DesignExamples.asp

I looked at the traffic lights demo (still shaking) and the Int_divide files. I can 
easily see your point when their software converts

	if (!sensor1 && !sensor2) nstate = 5;

into

            n2 = ~ sensor2_n1;
            n1 = ~ sensor1_n1;
            n3 = n1 & n2;
            if (n3 == 1'b1)
            begin
               nstate = 3'b101;
            end

With tools this bad (in my personal never used it before style opinion) around its no wonder
you aren't keen on C to HDL tools. Hopefully I'll be able to change your views in a few weeks.

Paul

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