RE: [oc] Re: How to create such signal wave using VHDL?

["Martin.J Thompson" <Martin.J.Thompson@trw.com>]

>Martin,
>
>he didn't mention a reset pin, not everybody has them. ;-) Was rather 
>surprised that his zero signal state is infinitely long so maybe there
>isn't a reset pin that he forgot to mention?
>

Yeah, I'm stuck in a synthesisable mode at the moment (due to work), so I assumed it was more than a simulation only requirement :-)

Cheers,
Martin


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