RE: [oc] Re: How to create such signal wave using VHDL?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Martin,

he didn't mention a reset pin, not everybody has them. ;-) Was rather 
surprised that his zero signal state is infinitely long so maybe there
isn't a reset pin that he forgot to mention?

Scary?

Paul


> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Martin.J Thompson
> Sent: 14 December 2001 09:09
> To: cores@opencores.org
> Subject: [oc] Re: How to creat such signal wave using VHDL?
> 
> 
> How about
> process(clk,resetn)
>   variable count: integer range 0 to 1024
> begin
>   if resetn = '0' then
>     outsig <= '1';
>     count := 0;
>   elsif risiing_edge(clk) then
>     if count < count'high then
>       count := count + 1;
>     else
>       outsig <= '0';
>     end if;
>   end if;
> end process;
> 
> 
> No guarantees, straight off the top of my head, untested!
> 
> Cheers,
> Martin
> 
> 
> -- 
> Martin Thompson BEng(Hons) CEng MIEE
> TRW Conekt
> Stratford Road, Solihull, B90 4GW. UK
> Tel: +44 (0)121-627-3569 - martin.j.thompson@trw.com
> 
> 
> >>> zeyaohan@263.net 13 December 2001 07:52:46 >>>
> I meet such problem in using VHDL to creat such signal wave:
> 
> such as the following wave:
> firstly I think it's a easy problem, but I find that in IF centence, after some event it can not exit, do i need to use 
> Loop centence then use exit syntax?
> 
> 
> ----------------------\
> 					   \----------------------------------------------------
> |<---1024 CLK-------->| |<----------------Infinitely Long-------------------
> 
> my process is the following:
> 
> process(clk)
> begin
> 	if clk'event and clk='1' then
> ............
> ............
> ............
> 	end if;
> end process;
> 
> 
> B.R
> 		hanzy
> 
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