Re: [oc] Better VHDL tools anyone?

[John Clark <clarkjc@stny.rr.com>]

Paul,

You do realize that only a small subset of VHDL syntax can be synthesized 
into a netlist for hardware resources?  I don't know of any synthesis tool 
that can handle "wait" or "loop" because there's no way to infer a clock 
signal.

If you have it, take a look at appendix A of Peter J. Ashenden's book, _The 
Designer's Guide to VHDL_.  He takes a generic look at the capabilities of 
synthesis tools and the IEEE proposed standard for a common subset for all 
tools.

- John

At 02:48 PM 12/09/2001 +0000, Paul McFeeters wrote:
>can anyone suggest good free Windows based VHDL tools. I'm using Webpack 
>at the moment but every time I get some sample code it just won't compile. 
>My latest "banging head against wall" issues are:
>
>No "loop" statement support.
>No "wait" statement support, both "wait until" and "wait for" are not 
>supported.

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