RE: [oc] Sequential processing in VHDL? Whats the best way to do it?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Hi,

the original question was "Sequential processing in VHDL? Whats the best way
to do it?". Well I now have the answer, quite simple really. The answer is
"forget VHDL and just do it in Verilog". After all the crap I had from
Webpack for various reasons I decided to try Verilog instead. Now I'm not
going to use VHDL again as Verilog is just so much better. I wrote a small
program to flash the LED in Verilog to get to grips with the language. It
was easier than learning VHDL from scratch. Then with Damjan's kind
assistance converted my FSM test model into Verilog but unlike the VHDL
version this one works! LED on for 1 second, off for 7 as it should be.

So, sorry to everybody waiting for C-to-VHDL its now going to be
C-to-Verilog. I can bear Webpack errors like the need to manually specify a
BUFG element on the clock pin but not the fact that its VHDL code doesn't
work so Verilog it is from now on. How can you write programs when the
compiler won't compile it accurately?

Martin, I've included my latest FSM test program (now in Verilog). If you
know VHDL then its quite simple to understand Verilog, took me about an hour
to do this program from scratch (even with Webpack fighting me along the
way). I'll code the C-to-Verilog program in ANSI-C (wherever possible) so it
can be compiled under any O/S out there.

Paul McFeeters








module verilog(CLK0,LED);
    input CLK0;
    output LED; reg LED ;

wire CLK ;
reg [21:0] COUNT ;
reg slow_clock ;
reg [2:0] state ;
// Divide the external 4MHz clock by 2^23 with a counter to produce a 1Hz
clock (slow_clock)

BUFG U3 (.I(CLK0), .O(CLK));	// Fudge as Webpack doesn't include this as it
should

initial
begin
	// Can't have a reset pin function hence just one reason why Verilog	is
some much better than
	// VHDL, took me two days to find a way to do an init function in VHDL! 5
secs for this one
	COUNT = 22'b0 ;	// don't really need this but will leave it here for later
	state = 0 ;
end

always @(posedge CLK)
begin
	COUNT = COUNT + 1 ;
   slow_clock = COUNT[21] ;
end

always @(posedge slow_clock)
begin

	case (state)
		3'b000 :
			LED = 1 ;
		default :
			LED = 0 ;
	endcase
	state = state + 1 ;
end // *(posedge slow_clock)

endmodule













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