RE: [oc] Anyone using VHDL procedures with Xilinx Webpack?

[John Clark <clarkjc@stny.rr.com>]

Paul,

I recently opened a support case with Xilinx for issues similar to this 
with the Xilinx Synthesis Technology (XST) synthesis tool in WebPack.  They 
told me that XST has bugs with evaluating functions in constant 
expressions, and that a service pack is due out for it in February or March.

I would recommend using a commercial synthesis tool, and avoid Xilinx's 
home grown XST for now.

- John

At 02:48 AM 12/08/2001 +0000, Paul McFeeters wrote:
>Jim,
>
>here is my biggest and most complicated function to date. Most people will
>probably recognise it as a simple function to let me write a byte to an IDE
>device's register via the PIO scheme. As the other function contains only
>pin assignments and no conditional logic this is the likely cause of
>Webpacks failure to process the VHDL properly.
>
>impure function PIO_register_write ( p_DA : std_logic_vector (2 downto 0);
>p_cs : integer ;   p_data : std_logic_vector (7 downto 0)  ) RETURN bit is
>begin
>         DA              <= p_DA ;
>         if (p_cs = 1) then
>                 -- register is in block 1
>                 cs1n            <= '0' ;
>                 cs3n            <= '1' ;
>         else
>                 -- register must be in block 3
>                 cs1n            <= '1' ;
>                 cs3n            <= '0' ;
>         end if;
>         iocs16n  <= '1' ;       -- only 8 bit register transfers
>         hi_byte  <= (others => '0') ;
>         lo_byte         <=      p_data ;
>         return '1' ;
>end function PIO_register_write ;
>
>If you tell me where in this function the error maybe then I will be so much
>the wiser. I'm not using macros or any string substitution system. When
>having them as procedures failed miserably I converted them to functions
>(then impure functions) and just return a '1' every time to validate them as
>functions versus procedures. Even as functions they fail to compile due to
>"exceptional errors" reported by Webpack.
>
>I'm going to give up on coding VHDL by hand and just develop my Buffy-C
>(working title for my version of Handel-C) then I can write a bloody IDE
>interface in 30 minutes not 30 days (plus the C one will work). I've
>probably spent %5 of my VHDL time putting new lines into the VHDL file and
>the other 95% getting Webpack to allow it to compile. I realise I am a
>newbie at VHDL but as I think up all my new projects in C terms so I want to
>code it in C as well. Trying to convert mentally from C to VHDL is too much
>for my set-in-its-ways brain to handle.
>
>Paul
>
>PS The code generated by Buffy-C doesn't contain any functions/procedures
>and it never will until VHDL compilers can happily compile them.

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