[oc] RE: Question

[Clayton John-P26867 <John.Clayton@motorola.com>]

Hello Everyone,

I am currently trying to initialize some Xilinx block-RAMs in my Verilog code, using Xilinx Foundation 3.1i.
I followed the instructions which say to use:

//synopsys attribute <name> <value>

So, I ended up adding:

//synopsys attribute dp_ram_block_1/ram0/ram0/INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF"

But it does not seem to work.  Does anyone have an example of initializing Xilinx BLOCK RAMs for FPGA Express or Xilinx FND3.1i?
I am stuck.

- John Clayton

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