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Re: [oc] UART16550 core



Hi Igor

I can add the cycle signal if you like, the examples in the wishbone spec
don't have that
signal, it is probably why I didn't include it.

regards
Carl

----- Original Message -----
From: "Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>
To: <cores@opencores.org>
Sent: Wednesday, August 08, 2001 1:11 PM
Subject: RE: [oc] UART16550 core


> Hi, Carl,
>
> I noticed that CYCLE signal is missing in your WISHBONE interface.
>
> Regards,
> Igor
>
> > -----Original Message-----
> > From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> > Behalf Of Carl van Schaik
> > Sent: 07. avgust 2001 8:04
> > To: cores@opencores.org
> > Subject: Re: [oc] UART16550 core
> >
> >
> > Hi Igor,
> >
> > > so if I understand correctly, there are two versions, one in
> > Verilog that
> > > was downloaded
> > > from the opencores and one in VHDL that you wrote (perhaps
> > opencores files
> > > translated to
> > > VHDL and than changed).
> > This is correct except that the Verilog was not simply converted to
VHDL.
> > I have written UART's before and used the Verilog code mainly as
> > an example
> > for my own code for the 16550.
> >
> > > I don't know which ones to take for testing. I'm a verilog guy,
> > not VHDL,
> > > although I would
> > > take the VHDL files if they contain less bugs than the ones in
verilog.
> >
> > Well, from what I saw, the Verilog version has a few bugs. The main ones
I
> > noticed are:
> >
> > FIFO - not cleared when data is popped out(empty). - Error bits
> > could remain
> > Break detection looked a bit weird (but I'm not a Verilog person)
> > Stop_bits signal in LCR(Line control register) is not used.
> > Only 16550 mode is supported, not 16540.
> > Break error is not passed through the FIFO!
> > Reciever will continue to recieve (0's) after a break is detected.
> >
> > > Can you tell me if I'm correct about the differences.
> > >
> > > In the meantime I'll start with the Verilog files.
> > >
> > > Regards,
> > > Igor
> >
> > regards
> > Carl
> >
> > --
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