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Re: [oc] RE: A core which I have implemented.
Hi John,
it is just a matter of changing your permissions. While I was typing
previous sentence I already changed your permissions.
Regarding rs232_syscon. Idea is really cool. With new permissions you have
ability to create new projects. Go ahead and don't be shy. :-)
regards,
Damjan
----- Original Message -----
From: "Clayton John-P26867" <John.Clayton@motorola.com>
To: <cores@opencores.org>
Sent: Wednesday, August 08, 2001 7:55 PM
Subject: [oc] RE: A core which I have implemented.
> Hello,
>
> My name is John Clayton. I have been looking at the opencores.org
web-page for over a year now, but I have been actively contributing (in a
small way) to the nnARM project (proof-reading documentation mostly) during
the past few weeks only. Now, I would like to add a project of my own. Do
I need to ask the webmaster to increase my access rights? I might only have
access to the nnARM area.
>
> I have been coding a core for use as a "debugging aid," and now that it is
done being coded and it seems to work, I would like to see about
contributing it. I still need to write the documentation, but that should
be fairly easy to do. The core is written in Verilog, just over 1000 lines
of code. I want to publish it in case someone else could get some use out
of it. I spent many hours debugging it.
>
> However, there is a "down" side to this core. because it uses serial
ports, each new serial bit emerges after many clock cycles, and I was
hesitant to run long simulations to verify my work. (Too many clock cycles!
Or maybe I am just too lazy!) That means there is no testbench with this
core. I did all of my debugging on an actual Xilinx XC2S200 FPGA, and used
a logic analyzer to see the signals directly. For me, this method was much
quicker than running simulations. This core _does_ work quite well on my
target board. However, I tried to keep the code portable, and I didn't use
any architecture-specific features of my target FPGA at all.
>
> I already have an account on Opencores. I just wanted to see what I
should do in order to begin sharing this design as a separate project. I
would like to call it "rs232_syscon" -- a debugging tool.
>
> If you want, you can send email to jclaytons@opencores.org. I think that
alias is still working! Otherwise, just reply to this address. Please let
me know how I can post this as a new project.
> Regards,
>
> John Clayton
>
>
> This is a more description of the core, and what it does:
>
> The core is called "rs232_syscon." It is a Wishbone (tm) compatible core
that allows the user to connect an rs232 terminal (so called "dumb
terminal") to the FPGA, and issue commands to configure the other target
devices inside of an FPGA. This helps in debugging, because you can program
registers and look at their contents without having to use a JTAG pod and
emulator software. All you need is an rs232 ASCII terminal and you can
program registers inside of your FPGA. In fact, you can hook up this core,
and exercise your Wishbone peripheral on the bus, with or without having a
processor attached, and without using a logic analyzer or other expensive
equipment.
>
> If it still sounds interesting, read on:
>
> A "master bus request" and "master bus grant" handshaking protocol is
provided so that the rs232_syscon can "request permission" to operate on the
bus. That feature has not been tested in actual practice yet -- I am still
deciding which processor to implement! But, in the absence of another bus
master, the unit can operate by itself, to program memory and/or registers
within your FPGA. It uses a tri-stated data bus instead of the split
"dat_o" and "dat_i" buses. Tri-state is allowed in Wishbone, but if you
prefer the split bus, you can easily modify this core to provide separate
buses.
>
> The rs232_syscon core does not have a processor in it (although in the
future I thought of making one with a very small microcontroller instead of
a state machine. It would be more flexible and extensible that way...)
Since it does not have a processor in it, and no software, the command
structure is kept very small... There are three commands: "read" "write"
and "initialize" (reset). That's it.
>
> However, it does have a "quantity" field in the commands, to make them
operate more than once. For instance the command "r 1000 80" will read 128
times, at sequential addresses starting with 1000 (hex). It formats the
data to the terminal window, showing the data in a nice readable hexadecimal
format. There is no support for showing data as ASCII characters...
>
> At the end of this email is a text sample of an actual debugging session
which I was running yesterday, using rs232_syscon to program some registers
which control an LCD panel and some LEDs on my Xilinx SpartanII board. The
rs232_syscon gives visual feedback concerning the Wishbone "ack_i" and
"err_i" signals, to indicate if an error was received on the Wishbone bus.
There is a watchdog timer which you can configure to "timeout" if no ack_i
is received, and it responds with "!"
>
> Also, the commands are parsed, with error messages to tell you if you
entered an invalid command, address, data or quantity field. The responses
for those errors are C?, A?, D? and Q?, respectively.
>
> Backspaces are supported, and the module is fully parameterized, so you
can configure it to use any bus width you want: 16-bit address with 32-bit
data, or else 32-bit address with 16-bit data. Any combination!!! However,
you will have to adjust the parameters, and the size of the module will
change significantly for larger bus sizes. However, that should be fine --
anyone using a 64-bit address and data bus (or larger) probably has a rather
large FPGA to run it on...
>
> This is a low level tool. Only one size of data element is supported --
the full size of the data bus chosen. (you must choose using parameters at
compile time.) There is NO support for little/big endian changing or
anything else fancy.
>
>
> rs232_syscon session follows (this one uses 16-bit address and 16-bit
data):
> -----------------------------------------------
> -> 0123456789ABCDEF
> -> w 1 55 1
> OK
> -> w 1 5a
> OK
> -> w 4 4c
> OK
> -> w 2 140
> OK
> -> w 3 100
> OK
> -> w 4 5c
> OK
> -> w 4 6c
> OK
> -> w 2 150
> OK
> -> w 3 f8
> OK
> -> w 3 f0
> OK
> -> w 3 f8
> OK
> -> w 3 f7
> OK
> -> w 3 48
> OK
> -> r 3
> 0003 : 0048 OK
> -> r 0 8
> 0000 : 0000 005A 0150 0048 006C 0000 0000 0000
> OK
> -> r 0 10
> 0000 : 0000 005A 0150 0048 006C 0000 0000 0000
> 0008 : 0000 005A 0150 0048 006C 0000 0000 0000
> OK
> -> r 0 20
> 0000 : 0000 005A 0150 0048 006C 0000 0000 0000
> 0008 : 0000 005A 0150 0048 006C 0000 0000 0000
> 0010 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
> 0018 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
> OK
> -> w 3 58
> OK
> -> w 3 68
> OK
> -> r 0 10
> 0000 : 0000 0068 0068 0068 0068 0068 0068 0068
> 0008 : 0000 0068 0068 0068 0068 0068 0068 0068
> OK
> -> w 3 58 1
> OK
> -> w 4 68 1
> OK
> -> r 0 10
> 0000 : 0000 0068 0068 0058 0068 0068 0068 0068
> 0008 : 0000 0068 0068 0058 0068 0068 0068 0068
> OK
> -> w 4 6c 1
> OK
> -> w 4 7c 1
> OK
> -> w 1 f4 1
> OK
> -> r 0 8
> 0000 : 0000 00F4 0068 0058 007C 0068 0068 0068
> OK
>
>
>
>
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