Re: [oc] UART16550 core

["Carl van Schaik" <carl@openfuel.com>]

Hi Igor

Maybe I should just send you the VHDL code. Add it to opencores?
I will need to clean up my code a bit, add some comments and the GPL
license first.

I have not tested the UART fully and I'm sure there are still lots of errors
in my VHDL.
Someone will need to add the Modem control lines part, but that should
not be too difficult.

I did not change any of the verilog code for the UART16550 on opencores
though. The verification module should work for both the VHDL and Verilog
implementations?

regards
Carl

> Hi, Carl,
>
> can you tell me what changes you did in the UART. I'm writing a
verification
> module.
> I already started but I don't want to change things you tested already and
> think are
> OK.
>
> Regards,
> Igor
>
> > -----Original Message-----
> > From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> > Behalf Of Carl van Schaik
> > Sent: 01. avgust 2001 7:29
> > To: cores@opencores.org
> > Subject: Re: [oc] UART16550 core
> >
> >
> > Hi
> >
> > I checked through the uart16550 code, looks like it needs a few changes.
> > I have writen a VHDL 16550 uart that I was going to post up along with
> > the Verilog version. It is currently working on my board so at
> > least I know
> > for sure that part of it works :-)  I just need to implement modem
control
> > lines (or any volunteers?, should be easy) and get around to posting it.
> >
> > regards
> > Carl van Schaik
> > --
> > Embedded Engineer
> > OpenFuel Pty Ltd.
> >
> > > Hi, Guys and girls (if any).
> > >
> > > I would like to know if anybody tested the UART16550 core so far.
> > > If any body implemented the core, run it on a board, etc...
> > >
> > > I want to help verifying the core.
> > >
> > > Regards,
> > > Igor
> > > --
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> > >
> >
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