[oc] synthesis problem with uart16550 core

[Matthias Fuchs <matthias.fuchs@esd-electronics.com>]

Hi,

I am trying to evaluate the uart16550 core on a SpartanII XC2S50 FPGA. I
got an error during synthesis of the
UART_transmitter module. My synthesis tool is XST from the Xilinx
Webpack Software. Here is the synthesis log output:

...
Starting low level synthesis...
Optimizing unit <UART_FIFO> ...

Optimizing unit <LPM_XOR5_1> ...

Optimizing unit <UART_transmitter> ...

WARNING : (FCT__0306). Multi-source on signal <shift_out<0>> not
replaced by logic
WARNING : (FCT__0306). Multi-source on signal <shift_out<1>> not
replaced by logic
WARNING : (FCT__0306). Multi-source on signal <shift_out<2>> not
replaced by logic
WARNING : (FCT__0306). Multi-source on signal <shift_out<3>> not
replaced by logic
WARNING : (FCT__0306). Multi-source on signal <shift_out<4>> not
replaced by logic
WARNING : (FCT__0306). Multi-source on signal <shift_out<5>> not
replaced by logic
ERROR : (SYNTH__0026). Synthesis failed
...

I cannot understand what went wring here. All other modules are fine !

Any idea ?

Matthias

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\ Matthias Fuchs                                 \
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