Re: [oc] Verilog Preprocessor

[Rudolf Usselmann <rudi@asics.ws>]

on 5/10/01 9:18, Lawrence Butcher at Lawrence.Butcher@Sun.COM wrote:

> Dont.  DONT!
> 
> That way, your code will only be usable wherever the preprocessor is.
> 
> I am a big fan of straight Verilog (no PLI, no pre-processor).
> 
> Unless the pre-processor is available by at most 2 clocks
> from where the Verilog is!
> 
> Lawrence

Lawrance,

I totally agree with you !

Here is the problem I'm having: All of my cores are configurable.
Most of the configuration options are achieved by using "`ifdef"
and "`ifndef". Some by using parameters.

It appears that some synthesis tools, can not handle these
statements. That's why I was looking for a pre processor, hoping
it would get rid of those. Don't worry, I won't add anything
that is outside of OVL ! All Verilog simulators I have used
seem not to have any problems with 'ifdefs.

In the men time, I did find "vpp". However, it does not get
rid of the 'ifdef, only of `ifndef. BTW: Vpp is free, and
runs an linux (and I presume any other unix). Source code
can be found on the net ...


Cheers !
-- 
rudi@puzzled