Re: [oc] Some code to be OpenCores

["Damjan Lampret" <lampret@opencores.org>]

> One is a monitor controller core. This core is capable of driving
> (after signal-level adjustment) Hercules, CGA, EGA, VGA monitors. It
> supports up-to 8-bit/pixel color depth and no capable of running
> ~60MHz pixel-clock in an Altera 1k30 device. The core is Wishbone
> compatible.

I think Richard Herveille would be interested to exchange a word with you
about this core. He also started working on VGA core. However he is
interested to support LCDs as well.

>
> The other is a toolkit initiative for Wishbone core designs. It should
> contain things like bus arbiters, simple peripherials, memories,
> FIFOs, bus resizers, bridges etc. All the useful stuff often needed
> when doing SoC. Currently it contains four simple cores and a huge
> wish-list.

Definately useful and good companion to Winefred Washington's Verilog
version. You can find his code in OpenCores CVS under wb_verilog directory.

> If you provide me the details I would like to put the stuff under
> OpenCores.
>

Sure, the procedure is very simple. Just send an email with your preferred
username for the CVS/webeditor account in private email and I'll make sure
you get it in a matter of hours. Once you have a CVS/webeditor account, you
can create new web pages and write to the OpenCores CVS.

regards,
Damjan