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[oc] SoC bus review

To: <cores@opencores.org>
Subject: [oc] SoC bus review
From: Rudolf Usselmann <rudi@asics.ws>
Date: Tue, 02 Jan 2001 23:02:26 +0700
In-Reply-To: <000901c074c5$3134d820$3d3bc089@hmf8h>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org
User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022


Attached is a small doc I created of three SoC busses.

It is basically a comparison, and my personal feelings about
the three busses.

I would welcome any comments and suggestions as well as a
friendly discussion on the doc !

Hopefully we can all agree on one SoC bus and jointly use it for
all future core developments.

Best Regards,
rudi

Follow-Ups:
- [oc] Wishbone historical perspective and a proposal to the OpenCores group
  - From: "Wade D. Peterson" <wadep@silicore.net>
- Re: [oc] SoC bus review
  - From: "Richard Herveille" <Richard.Herveille@pie.nl>
- Re: [oc] SoC bus review
  - From: John Dalton <johnd@southern-poro.com>

References:
- Re: [oc] I'd be happy to participate and answer WISHBONE relatedquestions.
  - From: "Wade D. Peterson" <wadep@silicore.net>

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