Re: [oc] Wishbus Bus

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi,
I agree with you that the master has to know the bus
width but since you are talking about bridge, it has
to know both sides and know how to convert it anyhow.

Also you can not make all cores 32 bits becuase you
have to put the conversion inside each block

Also I do not remember the Wishbus (I read it in the
past) but I remember that there was different bus
sizes.

Regards
Jamil Khatib

--- Winefred Washington <wwashington@austin.rr.com>
wrote:
> We may need to make an additional requirement to the
> Wishbone spec or
> perhaps Silicore is already working on it.
> 
> I was working on a simple testbench and here's the
> problem I think I found.
> A master device has to know what the bus width of
> the slave device is for
> the transfer to work correctly. Suppose we have a
> 32-bit PCI to Wishbone
> device and it has to transfer data to 32-bit  and an
> 8-bit devices. The PCI
> core has to change how the data is presented on the
> bus to match the data
> width of the slave devices. That means the PCI core
> has to contain logic
> specific to the application which hurts reuse.
> 
> One solution is to fix the data widths to 32-bits
> for all cores.
> 
> Any comments?
> 
> Did I miss something in the spec?
> 
> WW
> 
> 


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