Re: [oc] USB Core

["Guoqing Zhang" <gxz0233@hotmail.com>]

that's a good news. I started to write some code(verilog) from last week. I 
got some free evaluation codes(VHDL) from commercial sites and trying to 
understand its protocol. I'd like to work with you guys and make efforts to 
the development.

Guoqing Zhang

>From: Rudolf Usselmann <rudi@asics.ws>
>Reply-To: cores@opencores.org
>To: <usb@opencores.org>, <cores@opencores.org>
>Subject: [oc] USB Core
>Date: Sat, 30 Dec 2000 14:22:16 +0700
>
>
>I have started the development of USB cores. First I will design a
>USB function core, later a UCB host core. All of my designs (as always)
>will be in Verilog.
>
>I will be publishing a proposed specification within the next 2 weeks.
>
>If you are interested in it and other USB activities/discussion, please
>join the USB forum.
>
>rudi
>

_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com