Re: [oc] ATA-3 (EIDE) Opencore

[Rudolf Usselmann <rudi@asics.ws>]

Winefred,

I'm not sure about the status of the IDE core, may be Damjan can fill
that in.

For the internal IP bus, we are leaning towards Wishbone. The decision is
not final yet, but I think there are no alternatives. All other either
require a license or fees.

Wishbone can be found at:
http://www.silicore.net/pdfiles/wishbone.pdf

Best Regards,
rudi

on 12/29/00 22:25, Winefred Washington at wwashington@austin.rr.com wrote:
> Hello,
> 
> If the design in still open, I'd like to develop the IDE core. I'm an EE
> with Verilog experience. I also have several years of experience with Xilinx
> Virtex FPGAs. I don't have much experience with CVS, but I do have a book.
> 
> Is there a specification for an internal IP bus to connect various cores
> together?
> 
> Thanks in advance,
> WW
> 
> 
> 
>