head 1.1; branch 1.1.1; access; symbols version_1_1:1.1.1.1 okinawa_1:1.1.1.1 VSFR_1:1.1.1.1 Vectra:1.1.1; locks; strict; comment @# @; 1.1 date 2005.01.04.02.05.58; author arif_endro; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2005.01.04.02.05.58; author arif_endro; state Exp; branches; next ; desc @@ 1.1 log @Initial revision @ text @# $Id$ # Modelsim do file destroy .wave; destroy .list; vlib work; vcom fm_timesim.vhd bench_xil.vhdl input_fm_xil.vhdl; vsim -t 1ps bench; add wave /bench/clock; add wave /bench/reset; add wave -height 80 -scale .1 -format Analog-Step /bench/myfm/fmin add wave -height 80 -scale 2. -format Analog-Step /bench/myfm/dmout # force -freeze sim:/bench/clock 1 0, 0 {50 ns} -r 100 # force -freeze sim:/bench/reset 0 0 # run -all # run 102400ns @ 1.1.1.1 log @Initial releases @ text @@