head 1.1;
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1.1
date 2008.04.08.20.00.14; author fpga_is_funny; state Exp;
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1.1.1.1
date 2008.04.08.20.00.14; author fpga_is_funny; state Exp;
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1.1
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@Initial revision
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R6502_TC\Core\symbol_sb
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1.1.1.1
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@First Revision
After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile
The CVS history in the VHDL files is fine now.
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