head 1.3; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.3 date 2008.04.17.18.39.25; author fpga_is_funny; state Exp; branches; next 1.2; commitid 5a04480797854567; 1.2 date 2008.04.08.21.17.11; author fpga_is_funny; state Exp; branches; next 1.1; commitid 48f547fbdefd4567; 1.1 date 2008.04.08.20.00.03; author fpga_is_funny; state Exp; branches 1.1.1.1; next ; commitid 2b3f47fbcb9e4567; 1.1.1.1 date 2008.04.08.20.00.03; author fpga_is_funny; state Exp; branches; next ; commitid 2b3f47fbcb9e4567; desc @@ 1.3 log @Bugfixes for all relationchips with interrupts BRK, IRQ and NMI. The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down. The "B" status flag was never set within BRK. The relationchip between addresses and data while writing onto the stack was badly misalligned. @ text @ R6502_TC\Core\struct_bd

Generation Settings

Component declarationsyes
Configurationsembedded statements
add pragmas
exclude view name

Declarations

Ports:

clk_clk_i          : std_logic
d_i                : std_logic_vector(7 DOWNTO 0)
rdy_i              : std_logic
irq_n_i            : std_logic
so_n_i             : std_logic
a_o                : std_logic_vector(15 DOWNTO 0)
d_o                : std_logic_vector(7 DOWNTO 0)
rd_o               : std_logic
wr_o               : std_logic
wr_n_o             : std_logic
sync_o             : std_logic
rst_rst_n_i        : std_logic
nmi_n_i            : std_logic

Diagram Signals:

signal adr_o_i            : std_logic_vector(15 DOWNTO 0)
signal offset_o_i         : std_logic_vector(15 DOWNTO 0)
signal ch_a_o_i           : std_logic_vector(7 DOWNTO 0)
signal ch_b_o_i           : std_logic_vector(7 DOWNTO 0)
signal reg_0flag_core_o_i : std_logic
signal reg_3flag_core_o_i : std_logic
signal reg_7flag_core_o_i : std_logic
signal adr_sp_o_i         : std_logic_vector(15 DOWNTO 0)
signal adr_pc_o_i         : std_logic_vector(15 DOWNTO 0)
signal load_regs_o_i      : std_logic
signal ld_o_i             : std_logic_vector(1 DOWNTO 0)
signal reg_0flag_o_i      : std_logic
signal reg_1flag_o_i      : std_logic
signal reg_6flag_o_i      : std_logic
signal reg_7flag_o_i      : std_logic
signal d_regs_out_o_i     : std_logic_vector(7 DOWNTO 0)
signal d_alu_o_i          : std_logic_vector(7 DOWNTO 0)
signal cout_pc_o_i        : std_logic
signal sel_reg_o_i        : std_logic_vector(1 DOWNTO 0)
signal ld_pc_o_i          : std_logic
signal sel_alu_out_o_i    : std_logic_vector(2 DOWNTO 0)
signal sel_rb_out_o_i     : std_logic_vector(2 DOWNTO 0)
signal sel_rb_in_o_i      : std_logic_vector(2 DOWNTO 0)
signal sel_pc_in_o_i      : std_logic_vector(1 DOWNTO 0)
signal ld_sp_o_i          : std_logic
signal sel_sp_in_o_i      : std_logic_vector(1 DOWNTO 0)
signal sel_sp_val_o_i     : std_logic_vector(1 DOWNTO 0)
signal sel_pc_val_o_i     : std_logic_vector(1 DOWNTO 0)
signal sel_sp_as_o_i      : std_logic
signal sel_pc_as_o_i      : std_logic
signal sel_alu_as_o_i     : std_logic
signal adr_nxt_pc_o_i     : std_logic_vector(15 DOWNTO 0)
signal adr_nxt_sp_o_i     : std_logic_vector(15 DOWNTO 0)
signal q_a_o_i            : std_logic_vector(7 DOWNTO 0)
signal q_x_o_i            : std_logic_vector(7 DOWNTO 0)
signal q_y_o_i            : std_logic_vector(7 DOWNTO 0)
signal rst_rst_int_o_i    : std_logic
signal d_regs_in_o_i      : std_logic_vector(7 DOWNTO 0)
signal nmi_o_i            : std_logic
signal fetch_o_i          : std_logic

Pre User:



Post User:




Package List


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


Bundles














@


1.2
log
@Corrected HTML files for documentation (change $log$ to $Log$ in all VHDL files in first release)
@
text
@d7 1
a7 1

a58 1
nmi_i              : std_logic
d66 2
a67 1
rst_rst_n_i        : std_logic
d107 3
a109 1
signal d_regs_in_o_i      : std_logic_vector(7 DOWNTO 0)
@


1.1
log
@Initial revision
@
text
@d7 1
a7 1

@


1.1.1.1
log
@First Revision
After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile
The CVS history in the VHDL files is fine now.
@
text
@@