head 1.3; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.3 date 2008.04.17.18.39.25; author fpga_is_funny; state Exp; branches; next 1.2; commitid 5a04480797854567; 1.2 date 2008.04.08.21.17.11; author fpga_is_funny; state Exp; branches; next 1.1; commitid 48f547fbdefd4567; 1.1 date 2008.04.08.19.59.26; author fpga_is_funny; state Exp; branches 1.1.1.1; next ; commitid 2b3f47fbcb9e4567; 1.1.1.1 date 2008.04.08.19.59.26; author fpga_is_funny; state Exp; branches; next ; commitid 2b3f47fbcb9e4567; desc @@ 1.3 log @Bugfixes for all relationchips with interrupts BRK, IRQ and NMI. The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down. The "B" status flag was never set within BRK. The relationchip between addresses and data while writing onto the stack was badly misalligned. @ text @ R6502_TC\ALU\struct_bd

Generation Settings

Component declarationsyes
Configurationsembedded statements
add pragmas
exclude view name

Declarations

Ports:

ch_a_i           : std_logic_vector(7 DOWNTO 0)
ch_b_i           : std_logic_vector(7 DOWNTO 0)
d_alu_o          : std_logic_vector(7 DOWNTO 0)
reg_1flag_o      : std_logic
reg_0flag_o      : std_logic
reg_6flag_o      : std_logic
reg_7flag_o      : std_logic
reg_0flag_core_i : std_logic
reg_3flag_core_i : std_logic
sel_alu_as_i     : std_logic
reg_7flag_core_i : std_logic
sel_alu_out_i    : std_logic_vector(2 DOWNTO 0)

Diagram Signals:

signal q_and            : std_logic_vector(7 DOWNTO 0)
signal q_or             : std_logic_vector(7 DOWNTO 0)
signal q_xor            : std_logic_vector(7 DOWNTO 0)
signal q_aneg           : std_logic_vector(7 DOWNTO 0)
signal q_bneg           : std_logic_vector(7 DOWNTO 0)
signal val_zero         : std_logic_vector(7 DOWNTO 0)
signal val_one          : std_logic_vector(7 DOWNTO 0)
signal val_two          : std_logic_vector(7 DOWNTO 0)
signal q_a              : std_logic_vector(7 DOWNTO 0)
signal din              : std_logic
signal din1             : std_logic
signal sel              : std_logic_vector(1 DOWNTO 0)
signal din0             : std_logic
signal din2             : std_logic
signal din3             : std_logic
signal dout             : std_logic

Pre User:



Post User:




Package List


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


Bundles














@


1.2
log
@Corrected HTML files for documentation (change $log$ to $Log$ in all VHDL files in first release)
@
text
@d7 1
a7 1

@


1.1
log
@Initial revision
@
text
@d7 1
a7 1

@


1.1.1.1
log
@First Revision
After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile
The CVS history in the VHDL files is fine now.
@
text
@@