The zipped CD16 archive contains:
| Folder | Contents | Notes |
| /CD16 //4th //Doc ///AnsDraft ///Raptor ///web //Xilinx |
VHDL source code for a demo system Source code for compiler and simulator Documentation ANS Forth draft Standard dpans.htm Some compiler documentation This page and documentation Xilinx-specific SoC implementation |
1. 2. 3. |
Notes:
1. Synthesizable VHDL of a demo system with a testbench. You can run this with any VHDL simulator. You could synthesize it too, but the stack memory won't synthesize efficiently with most tools. You can manually instantiate the memories for the FPGA or ASIC you intend to use. The testbench contains ASSERT statements to verify that the VHDL model matches the Forth model. If you run the model with ModelSim or some other simulation tool, set the default compiler options to "Use explicit declarations". The testbench also likes "Use 1993 language syntax". The simulator should be set to break on Error.
2. The compiler runs under Win32forth. To compile or simulate code you need to install Win32forth on your system. Once Win32forth is installed and launched, you can use the file menu to load R.F. Then load CD16.F (or your source file) to generate ROM.HEX. ROM.TXT is a disassembled version of the whole ROM, while ROM.LAB is a label file used by the simulator.
You can load SIM.F to start the simulator. Relaunch Win32forth first. The console window will be
available for testing. Use the Q command to exercise a line of Forth code. For
example, Q 1 2 OVER +. The simulator can be used to generate a new
synthesizable ROM using "SYNSAVE
If you want a standalone simulator window, use "1 INCLUDE SIM.F" to generate a turnkey application. If you move the application, remember that it consists of SIM.EXE and SIM.IMG.
BENCH.F is a version of the simulator that runs under VFX or other ANS Forths. Very little user interface. I use it to compare simulation speeds against Win32forth. BENCHMK.ZIP is a really ANSified version with VHDL stripped off (using the FILTER.F utility). It's a nice acid test for Forth compilers. Type "25000000 BENCHMARK" to see how long one second of execution takes to simulate. Using VFX with no special settings, it took 47 seconds on a 1.8 GHz P4 running Windoze 2000.
3. This folder contains Xilinx specific instantiations of the memories. A system with these and the files in the CD16 folder synthesizes with Xilinx's ISE Webpack. The post-synthesis VHDL model of the demo SoC (fit into a XC2S50E-PQ208) works with the testbench BENCH.VHD so it should run in real hardware. A version DemoSocExt.vhd that uses off-chip program memory hasn't been tested.
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