------------------------------------------------------------------------------ -- Title : COUNTER_H -- Project : ROBOTIC ARM CONTROLLER ------------------------------------------------------------------------------- -- File : counter_h.vhd -- Author : R.SATHISH KUMAR -- Created : 25-4-2001 -- Last update : ------------------------------------------------------------------------------- -- Description: -- This vhdl module is a counter. -- for generation of half step control signals. ----------------------------------------------------------------------------- ------ counter_h library IEEE; use IEEE.std_logic_1164.all; use work.std_arith.all; entity counter_h is port(CLK : in STD_LOGIC; STEP_SEL:in STD_LOGIC; STOP :in STD_LOGIC; DOUT_H : buffer STD_LOGIC_VECTOR(2 downto 0)); end counter_h; architecture behave of counter_h is signal count_h : std_logic_vector(2 downto 0); begin process(CLK ,STOP,STEP_SEL) begin if(CLK 'event and CLK ='1')then if(STOP ='1')then count_h<=count_h; elsif(STEP_SEL = '0') then count_h<=count_h+1; end if; end if; DOUT_H<=count_h; end process; end behave;